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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen stable-4.1] x86/AMD: work around erratum 793 for 32-bit
commit 934858f00267a92bc2a2995a0c634d02d2c60fbd
Author: Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Thu Feb 20 08:43:11 2014 +0100
Commit: Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Thu Feb 20 08:43:11 2014 +0100
x86/AMD: work around erratum 793 for 32-bit
The original change went into a 64-bit only code section, thus leaving
the issue unfixed on 32-bit. Re-order code to address this.
This is part of CVE-2013-6885 / XSA-82.
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
Acked-by: Ian Campbell <Ian.Campbell@xxxxxxxxxx>
---
xen/arch/x86/cpu/amd.c | 24 ++++++++++++------------
1 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 54ca33c..e1190ef 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -649,6 +649,18 @@ static void __devinit init_amd(struct cpuinfo_x86 *c)
"*** Pass \"allow_unsafe\" if you're trusting"
" all your (PV) guest kernels. ***\n");
+ /* AMD CPUs do not support SYSENTER outside of legacy mode. */
+ clear_bit(X86_FEATURE_SEP, c->x86_capability);
+
+ if (c->x86 == 0x10) {
+ /* do this for boot cpu */
+ if (c == &boot_cpu_data)
+ check_enable_amd_mmconf_dmi();
+
+ fam10h_check_enable_mmcfg();
+ }
+#endif
+
if (c->x86 == 0x16 && c->x86_model <= 0xf) {
rdmsrl(MSR_AMD64_LS_CFG, value);
if (!(value & (1 << 15))) {
@@ -663,18 +675,6 @@ static void __devinit init_amd(struct cpuinfo_x86 *c)
}
}
- /* AMD CPUs do not support SYSENTER outside of legacy mode. */
- clear_bit(X86_FEATURE_SEP, c->x86_capability);
-
- if (c->x86 == 0x10) {
- /* do this for boot cpu */
- if (c == &boot_cpu_data)
- check_enable_amd_mmconf_dmi();
-
- fam10h_check_enable_mmcfg();
- }
-#endif
-
if (c->x86 == 0x10) {
/*
* On family 10h BIOS may not have properly enabled WC+
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.1
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