[Xen-changelog] [xen master] xen: arm: make stage 2 page tables walks inner-shareable

[patchbot@xxxxxxx]

commit 8200daed053bc7f3dca4ee5b42d9f84934b998d7
Author:     Ian Campbell <ian.campbell@xxxxxxxxxx>
AuthorDate: Mon Mar 17 17:27:40 2014 +0000
Commit:     Ian Campbell <ian.campbell@xxxxxxxxxx>
CommitDate: Tue Mar 18 15:55:28 2014 +0000

    xen: arm: make stage 2 page tables walks inner-shareable
    
    The comment was previously incorrect and indicated that these mappings were
    unshared (00) when in reality the register was set for outer-shareable (01).
    
    Clarify ORGN0/IRGN0 in the comments while at it.
    
    Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    Acked-by: Julien Grall <julien.grall@xxxxxxxxxx>
---
 xen/arch/arm/mm.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index e9b3f34..6f1408b 100644
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -378,16 +378,17 @@ void __init arch_init_memory(void)
 void __cpuinit setup_virt_paging(void)
 {
     /* Setup Stage 2 address translation */
-    /* SH0=00, ORGN0=IRGN0=01
+    /* SH0=11 (Inner-shareable)
+     * ORGN0=IRGN0=01 (Normal memory, Write-Back Write-Allocate Cacheable)
      * SL0=01 (Level-1)
      * ARVv7: T0SZ=(1)1000 = -8 (32-(-8) = 40 bit physical addresses)
      * ARMv8: T0SZ=01 1000 = 24 (64-24   = 40 bit physical addresses)
      *        PS=010 == 40 bits
      */
 #ifdef CONFIG_ARM_32
-    WRITE_SYSREG32(0x80002558, VTCR_EL2);
+    WRITE_SYSREG32(0x80003558, VTCR_EL2);
 #else
-    WRITE_SYSREG32(0x80022558, VTCR_EL2);
+    WRITE_SYSREG32(0x80023558, VTCR_EL2);
 #endif
     isb();
 }
--
generated by git-patchbot for /home/xen/git/xen.git#master

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