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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen master] hvmloader: PA range 0xfc000000-0xffffffff should be UC
commit c22bd567ce22f6ad9bd93318ad0d7fd1c2eadb0d
Author: Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Wed May 21 18:14:04 2014 +0200
Commit: Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Wed May 21 18:14:04 2014 +0200
hvmloader: PA range 0xfc000000-0xffffffff should be UC
Rather than leaving the range from PCI_MEM_END (0xfc000000) to 4G
uncovered, we should include this in the UC range created for the (low)
PCI range. Besides being more correct, this also has the advantage that
with the way pci_setup() currently works the range will always be
mappable with a single variable range MTRR (rather than from 2 to 5
depending on how much the lower boundary gets shifted down to
accommodate all devices).
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
---
tools/firmware/hvmloader/cacheattr.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/firmware/hvmloader/cacheattr.c
b/tools/firmware/hvmloader/cacheattr.c
index e7c219f..de8d39c 100644
--- a/tools/firmware/hvmloader/cacheattr.c
+++ b/tools/firmware/hvmloader/cacheattr.c
@@ -99,12 +99,12 @@ void cacheattr_init(void)
{
uint64_t base = pci_mem_start, size;
- for ( i = 0; (base != pci_mem_end) && (i < nr_var_ranges); i++ )
+ for ( i = 0; !(base >> 32) && (i < nr_var_ranges); i++ )
{
size = PAGE_SIZE;
while ( !(base & size) )
size <<= 1;
- while ( ((base + size) < base) || ((base + size) > pci_mem_end) )
+ while ( ((base + size) < base) || ((base + size - 1) >> 32) )
size >>= 1;
wrmsr(MSR_MTRRphysBase(i), base);
--
generated by git-patchbot for /home/xen/git/xen.git#master
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