[Xen-changelog] [xen master] tools/mce: add more MCE types to xen-mceinj

[patchbot@xxxxxxx]

commit 4b3b9d3e1922177cc1a5a5218c11dc4e18e3ebc0
Author:     David Vrabel <david.vrabel@xxxxxxxxxx>
AuthorDate: Mon Jun 23 18:57:01 2014 +0100
Commit:     Ian Campbell <ian.campbell@xxxxxxxxxx>
CommitDate: Fri Jun 27 14:13:24 2014 +0100

    tools/mce: add more MCE types to xen-mceinj
    
    Add a non-fatal MCE for AMD CPUs.
    
    Add a fatal (PCC set) MCE for Intel CPUs.
    
    Signed-off-by: David Vrabel <david.vrabel@xxxxxxxxxx>
    Acked-by: Christoph Egger <chegger@xxxxxxxxx>
    Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
---
 tools/tests/mce-test/tools/xen-mceinj.c |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/tools/tests/mce-test/tools/xen-mceinj.c 
b/tools/tests/mce-test/tools/xen-mceinj.c
index 1f872a5..8ad045f 100644
--- a/tools/tests/mce-test/tools/xen-mceinj.c
+++ b/tools/tests/mce-test/tools/xen-mceinj.c
@@ -93,6 +93,22 @@ static struct mce_info mce_table[] = {
         .mci_misc = 0x86ull,
         .cmci = true,
     },
+    /* AMD L1 instruction cache data or tag parity. */
+    {
+        .description = "AMD L1 icache parity",
+        .mcg_stat = 0x5,
+        .bank = 1,
+        .mci_stat = 0x9400000000000151ull,
+        .mci_misc = 0x86ull,
+    },
+    /* LLC (Last Level Cache) EWB (Explicit Write Back) SRAO MCE */
+    {
+        .description = "MCE_SRAO_MEM (Fatal)",
+        .mcg_stat = 0x5,
+        .bank = 7,
+        .mci_stat = 0xBF2000008000017Aull,
+        .mci_misc = 0x86ull,
+    },
 };
 #define MCE_TABLE_SIZE (sizeof(mce_table)/sizeof(mce_table[0]))
 
--
generated by git-patchbot for /home/xen/git/xen.git#master

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