[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen master] xen/arm: vgic-v3: Correctly set GICD_TYPER.IDbits
commit 8206d052eb11061d7b6cada566c0804c14001fec Author: Julien Grall <julien.grall@xxxxxxxxxx> AuthorDate: Mon Feb 16 14:50:41 2015 +0000 Commit: Ian Campbell <ian.campbell@xxxxxxxxxx> CommitDate: Thu Feb 19 16:54:01 2015 +0000 xen/arm: vgic-v3: Correctly set GICD_TYPER.IDbits From Linux 3.19, the GICv3 drivers is using GICD_TYPER.IDbits to check the validity of the hardware interrupt number. The field IDBits in the register GICD_TYPER is used to know the number of interrupt identifiers (SPI, PPIs, SGIs, LPIs) supported by GIC Stream Protocol Interface. This field contains the number of interrupt identifier bits minus one. Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx> Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx> --- xen/arch/arm/vgic-v3.c | 11 +++++++++++ xen/include/asm-arm/gic_v3_defs.h | 3 +++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index bece189..72b22ee 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -679,11 +679,22 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info) vgic_unlock(v); return 1; case GICD_TYPER: + { + /* + * Number of interrupt identifier bits supported by the GIC + * Stream Protocol Interface + */ + unsigned int irq_bits = get_count_order(vgic_num_irqs(v->domain)); + if ( dabt.size != DABT_WORD ) goto bad_width; /* No secure world support for guests. */ *r = (((v->domain->max_vcpus << 5) & GICD_TYPE_CPUS ) | ((v->domain->arch.vgic.nr_spis / 32) & GICD_TYPE_LINES)); + + *r |= (irq_bits - 1) << GICD_TYPE_ID_BITS_SHIFT; + return 1; + } case GICD_STATUSR: /* * Optional, Not implemented for now. diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h index 13adb53..b8a1c2e 100644 --- a/xen/include/asm-arm/gic_v3_defs.h +++ b/xen/include/asm-arm/gic_v3_defs.h @@ -45,6 +45,9 @@ #define GICC_SRE_EL2_DIB (1UL << 2) #define GICC_SRE_EL2_ENEL1 (1UL << 3) +/* Additional bits in GICD_TYPER defined by GICv3 */ +#define GICD_TYPE_ID_BITS_SHIFT 19 + #define GICD_CTLR_RWP (1UL << 31) #define GICD_CTLR_ARE_NS (1U << 4) #define GICD_CTLR_ENABLE_G1A (1U << 1) -- generated by git-patchbot for /home/xen/git/xen.git#master _______________________________________________ Xen-changelog mailing list Xen-changelog@xxxxxxxxxxxxx http://lists.xensource.com/xen-changelog
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