[Xen-changelog] [qemu-xen-4.5-testing] The adjustments are solely to make the subsequent patches work right

[patchbot@xxxxxxx]

commit ec61b935a0eefbd0b6822e2b7bca958bb676bb40
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Tue Jun 9 16:32:24 2015 +0100
Commit:     Ian Jackson <Ian.Jackson@xxxxxxxxxxxxx>
CommitDate: Tue Jun 9 16:32:24 2015 +0100

    The adjustments are solely to make the subsequent patches work right
    (and hence make the patch set consistent), namely if permissive mode
    (introduced by the last patch) gets used (as both reserved registers
    and reserved fields must be similarly protected from guest access in
    default mode, but the guest should be allowed access to them in
    permissive mode).
    
    This is a preparatory patch for XSA-131.
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 hw/pass-through.c |   17 +++++++++++------
 hw/pass-through.h |    2 ++
 2 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/hw/pass-through.c b/hw/pass-through.c
index 67c0fd0..095d5a6 100644
--- a/hw/pass-through.c
+++ b/hw/pass-through.c
@@ -283,7 +283,7 @@ static struct pt_reg_info_tbl pt_emu_reg_header0_tbl[] = {
         .offset     = PCI_COMMAND,
         .size       = 2,
         .init_val   = 0x0000,
-        .ro_mask    = 0xF880,
+        .res_mask   = 0xF880,
         .emu_mask   = 0x0743,
         .init       = pt_common_reg_init,
         .u.w.read   = pt_word_reg_read,
@@ -310,7 +310,8 @@ static struct pt_reg_info_tbl pt_emu_reg_header0_tbl[] = {
         .offset     = PCI_STATUS,
         .size       = 2,
         .init_val   = 0x0000,
-        .ro_mask    = 0x06FF,
+        .res_mask   = 0x0007,
+        .ro_mask    = 0x06F8,
         .emu_mask   = 0x0010,
         .init       = pt_status_reg_init,
         .u.w.read   = pt_word_reg_read,
@@ -496,7 +497,8 @@ static struct pt_reg_info_tbl pt_emu_reg_pm_tbl[] = {
         .offset     = PCI_PM_CTRL,
         .size       = 2,
         .init_val   = 0x0008,
-        .ro_mask    = 0xE1FC,
+        .res_mask   = 0x00F0,
+        .ro_mask    = 0xE10C,
         .emu_mask   = 0x8100,
         .init       = pt_pmcsr_reg_init,
         .u.w.read   = pt_word_reg_read,
@@ -508,7 +510,8 @@ static struct pt_reg_info_tbl pt_emu_reg_pm_tbl[] = {
         .offset     = PCI_PM_CTRL,
         .size       = 2,
         .init_val   = 0x0008,
-        .ro_mask    = 0xE1FC,
+        .res_mask   = 0x00F0,
+        .ro_mask    = 0xE10C,
         .emu_mask   = 0x810B,
         .init       = pt_pmcsr_reg_init,
         .u.w.read   = pt_word_reg_read,
@@ -656,7 +659,8 @@ static struct pt_reg_info_tbl pt_emu_reg_msi_tbl[] = {
         .offset     = PCI_MSI_FLAGS, // 2
         .size       = 2,
         .init_val   = 0x0000,
-        .ro_mask    = 0xFF8E,
+        .res_mask   = 0xFE00,
+        .ro_mask    = 0x018E,
         .emu_mask   = 0x017E,
         .init       = pt_msgctrl_reg_init,
         .u.w.read   = pt_word_reg_read,
@@ -779,7 +783,8 @@ static struct pt_reg_info_tbl pt_emu_reg_msix_tbl[] = {
         .offset     = PCI_MSI_FLAGS, // 2
         .size       = 2,
         .init_val   = 0x0000,
-        .ro_mask    = 0x3FFF,
+        .res_mask   = 0x3800,
+        .ro_mask    = 0x07FF,
         .emu_mask   = 0x0000,
         .init       = pt_msixctrl_reg_init,
         .u.w.read   = pt_word_reg_read,
diff --git a/hw/pass-through.h b/hw/pass-through.h
index 5adc12d..ab27725 100644
--- a/hw/pass-through.h
+++ b/hw/pass-through.h
@@ -374,6 +374,8 @@ struct pt_reg_info_tbl {
     uint32_t size;
     /* reg initial value */
     uint32_t init_val;
+    /* reg reserved field mask (ON:reserved, OFF:defined) */
+    uint32_t res_mask;
     /* reg read only field mask (ON:RO/ROS, OFF:other) */
     uint32_t ro_mask;
     /* reg emulate field mask (ON:emu, OFF:passthrough) */
--
generated by git-patchbot for /home/xen/git/qemu-xen-4.5-testing.git

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