[Xen-changelog] [xen master] xen/arm: vgic-v2: Implement correctly ITARGETSR0 - ITARGETSR7 read-only

[patchbot@xxxxxxx]

commit bc50de883847c1ebc7c8b4d73283d9be6c4df38e
Author:     Julien Grall <julien.grall@xxxxxxxxxx>
AuthorDate: Wed Nov 18 16:42:38 2015 +0000
Commit:     Ian Campbell <ian.campbell@xxxxxxxxxx>
CommitDate: Wed Nov 25 11:56:35 2015 +0000

    xen/arm: vgic-v2: Implement correctly ITARGETSR0 - ITARGETSR7 read-only
    
    Each ITARGETSR register are 4-byte wide and the offset is in byte.
    
    The current implementation is computing the end of the range wrongly
    resulting to emulate only ITARGETSR{0,1} read-only. The rest will be
    treated as read-write.
    
    As 8 registers should be read-only, the end of the range should be
    ITARGETSR + (4 * 8) - 1.
    
    For convenience introduce ITARGETSR7 and ITARGETSR8.
    
    Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
    Reviewed-by: Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>
---
 xen/arch/arm/vgic-v2.c    |    4 ++--
 xen/include/asm-arm/gic.h |    2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c
index f7d784b..041291c 100644
--- a/xen/arch/arm/vgic-v2.c
+++ b/xen/arch/arm/vgic-v2.c
@@ -338,11 +338,11 @@ static int vgic_v2_distr_mmio_write(struct vcpu *v, 
mmio_info_t *info,
                v, r, gicd_reg - GICD_ICACTIVER);
         return 0;
 
-    case GICD_ITARGETSR ... GICD_ITARGETSR + 7:
+    case GICD_ITARGETSR ... GICD_ITARGETSR7:
         /* SGI/PPI target is read only */
         goto write_ignore_32;
 
-    case GICD_ITARGETSR + 8 ... GICD_ITARGETSRN:
+    case GICD_ITARGETSR8 ... GICD_ITARGETSRN:
     {
         /* unsigned long needed for find_next_bit */
         unsigned long target;
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index 0116481..3064d1c 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -42,6 +42,8 @@
 #define GICD_IPRIORITYR (0x400)
 #define GICD_IPRIORITYRN (0x7F8)
 #define GICD_ITARGETSR  (0x800)
+#define GICD_ITARGETSR7 (0x81C)
+#define GICD_ITARGETSR8 (0x820)
 #define GICD_ITARGETSRN (0xBF8)
 #define GICD_ICFGR      (0xC00)
 #define GICD_ICFGRN     (0xCFC)
--
generated by git-patchbot for /home/xen/git/xen.git#master

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