[Xen-changelog] [xen stable-4.6] x86/VPMU: don't allow any non-zero writes to MSR_IA32_PEBS_ENABLE

[patchbot@xxxxxxx]

commit ffb237937a38989e5d598e7774ad45791f164ae7
Author:     Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>
AuthorDate: Thu Jan 21 09:48:21 2016 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Thu Jan 21 09:48:21 2016 +0100

    x86/VPMU: don't allow any non-zero writes to MSR_IA32_PEBS_ENABLE
    
    Calculation reserved bits for MSR_IA32_PEBS_ENABLE is model-dependent
    and since we don't support PEBS anyway we shouldn't allow any writes to
    it (but let's still permit guests wishing to disable PEBS).
    
    We should also report PEBS as unsupported to HVM, just like we do on PV.
    
    Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>
    Acked-by: Kevin Tian <kevin.tian@xxxxxxxxx>
    master commit: fb424bf6b5b0df0155ab4e56a1b8f67e6470fa46
    master date: 2016-01-07 15:27:16 +0100
---
 xen/arch/x86/cpu/vpmu_intel.c |   13 ++++++-------
 1 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c
index 7a8c824..80eecc7 100644
--- a/xen/arch/x86/cpu/vpmu_intel.c
+++ b/xen/arch/x86/cpu/vpmu_intel.c
@@ -264,7 +264,6 @@ static void core2_vpmu_set_msr_bitmap(unsigned long 
*msr_bitmap)
          clear_bit(msraddr_to_bitpos(MSR_P6_EVNTSEL(i)), msr_bitmap);
 
     clear_bit(msraddr_to_bitpos(MSR_CORE_PERF_FIXED_CTR_CTRL), msr_bitmap);
-    clear_bit(msraddr_to_bitpos(MSR_IA32_PEBS_ENABLE), msr_bitmap);
     clear_bit(msraddr_to_bitpos(MSR_IA32_DS_AREA), msr_bitmap);
 }
 
@@ -296,7 +295,6 @@ static void core2_vpmu_unset_msr_bitmap(unsigned long 
*msr_bitmap)
         set_bit(msraddr_to_bitpos(MSR_P6_EVNTSEL(i)), msr_bitmap);
 
     set_bit(msraddr_to_bitpos(MSR_CORE_PERF_FIXED_CTR_CTRL), msr_bitmap);
-    set_bit(msraddr_to_bitpos(MSR_IA32_PEBS_ENABLE), msr_bitmap);
     set_bit(msraddr_to_bitpos(MSR_IA32_DS_AREA), msr_bitmap);
 }
 
@@ -367,7 +365,6 @@ static inline void __core2_vpmu_load(struct vcpu *v)
 
     wrmsrl(MSR_CORE_PERF_FIXED_CTR_CTRL, core2_vpmu_cxt->fixed_ctrl);
     wrmsrl(MSR_IA32_DS_AREA, core2_vpmu_cxt->ds_area);
-    wrmsrl(MSR_IA32_PEBS_ENABLE, core2_vpmu_cxt->pebs_enable);
 
     if ( !has_hvm_container_vcpu(v) )
     {
@@ -393,6 +390,8 @@ static int core2_vpmu_verify(struct vcpu *v)
         return -EINVAL;
     if ( core2_vpmu_cxt->global_ctrl & global_ctrl_mask )
         return -EINVAL;
+    if ( core2_vpmu_cxt->pebs_enable )
+        return -EINVAL;
 
     fixed_ctrl = core2_vpmu_cxt->fixed_ctrl;
     if ( fixed_ctrl & fixed_ctrl_mask )
@@ -603,10 +602,9 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t 
msr_content,
                  "MSR_PERF_GLOBAL_STATUS(0x38E)!\n");
         return -EINVAL;
     case MSR_IA32_PEBS_ENABLE:
-        if ( msr_content & 1 )
-            gdprintk(XENLOG_WARNING, "Guest is trying to enable PEBS, "
-                     "which is not supported.\n");
-        core2_vpmu_cxt->pebs_enable = msr_content;
+        if ( msr_content )
+            /* PEBS is reported as unavailable in MSR_IA32_MISC_ENABLE */
+            return -EINVAL;
         return 0;
     case MSR_IA32_DS_AREA:
         if ( vpmu_is_set(vpmu, VPMU_CPU_HAS_DS) )
@@ -728,6 +726,7 @@ static int core2_vpmu_do_rdmsr(unsigned int msr, uint64_t 
*msr_content)
         /* Extension for BTS */
         if ( vpmu_is_set(vpmu, VPMU_CPU_HAS_BTS) )
             *msr_content &= ~MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
+        *msr_content |= MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
     }
 
     return 0;
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.6

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