[Xen-changelog] [xen master] x86/PV: make PMU MSR handling consistent

[patchbot@xxxxxxx]

commit bea64b3ed25864b90a41e1ca6eeb5a58895bb751
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Fri Sep 2 14:19:29 2016 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Fri Sep 2 14:19:29 2016 +0200

    x86/PV: make PMU MSR handling consistent
    
    So far accesses to Intel MSRs on an AMD system fall through to the
    default case, while accesses to AMD MSRs on an Intel system bail (in
    the RDMSR case without updating EAX and EDX). Make the "AMD MSRs on
    Intel" case match the "Intel MSR on AMD" one.
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Reviewed-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>
    Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
 xen/arch/x86/traps.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 992ba23..d2f2de4 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2912,8 +2912,8 @@ static int emulate_privileged_op(struct cpu_user_regs 
*regs)
 
                     if ( vpmu_do_wrmsr(regs->ecx, msr_content, 0) )
                         goto fail;
+                    break;
                 }
-                break;
             }
             /*FALLTHROUGH*/
 
@@ -3048,8 +3048,8 @@ static int emulate_privileged_op(struct cpu_user_regs 
*regs)
 
                     regs->eax = (uint32_t)val;
                     regs->edx = (uint32_t)(val >> 32);
+                    break;
                 }
-                break;
             }
             /*FALLTHROUGH*/
 
--
generated by git-patchbot for /home/xen/git/xen.git#master

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