[Xen-changelog] [xen master] x86/AMD: apply erratum 665 workaround

[patchbot@xxxxxxx]

commit 6bfee2038565a208f4ecef0911087ca10eecf25b
Author:     Emanuel Czirai <icanrealizeum@xxxxxxxxx>
AuthorDate: Mon Sep 26 17:28:09 2016 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Mon Sep 26 17:28:09 2016 +0200

    x86/AMD: apply erratum 665 workaround
    
    AMD F12h machines have an erratum which can cause DIV/IDIV to behave
    unpredictably. The workaround is to set MSRC001_1029[31] but sometimes
    there is no BIOS update containing that workaround so let's do it
    ourselves unconditionally. It is simple enough.
    
    [ Borislav: Wrote commit message. ]
    
    Signed-off-by: Emanuel Czirai <icanrealizeum@xxxxxxxxx>
    Signed-off-by: Borislav Petkov <bp@xxxxxxx>
    [Linux commit: d1992996753132e2dafe955cccb2fb0714d3cfc4]
    
    Make applicable to Xen.
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
 xen/arch/x86/cpu/amd.c          | 12 ++++++++++++
 xen/include/asm-x86/msr-index.h |  3 ++-
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 2317546..4ff0b54 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -661,6 +661,18 @@ static void init_amd(struct cpuinfo_x86 *c)
                                       smp_processor_id());
                        wrmsrl(MSR_AMD64_LS_CFG, value | (1 << 15));
                }
+       } else if (c->x86 == 0x12) {
+               rdmsrl(MSR_AMD64_DE_CFG, value);
+               if (!(value & (1U << 31))) {
+                       static bool warned;
+
+                       if (c == &boot_cpu_data || opt_cpu_info ||
+                           !test_and_set_bool(warned))
+                               printk(KERN_WARNING
+                                      "CPU%u: Applying workaround for erratum 
665\n",
+                                      smp_processor_id());
+                       wrmsrl(MSR_AMD64_DE_CFG, value | (1U << 31));
+               }
        }
 
        /* AMD CPUs do not support SYSENTER outside of legacy mode. */
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index deb82a7..98dbff1 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -199,10 +199,11 @@
 
 /* AMD64 MSRs */
 #define MSR_AMD64_NB_CFG               0xc001001f
+#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT        46
 #define MSR_AMD64_LS_CFG               0xc0011020
 #define MSR_AMD64_IC_CFG               0xc0011021
 #define MSR_AMD64_DC_CFG               0xc0011022
-#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT        46
+#define MSR_AMD64_DE_CFG               0xc0011029
 
 #define MSR_AMD64_DR0_ADDRESS_MASK     0xc0011027
 #define MSR_AMD64_DR1_ADDRESS_MASK     0xc0011019
--
generated by git-patchbot for /home/xen/git/xen.git#master

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