[Xen-changelog] [xen master] x86/mce: clear MSR_IA32_MCG_STATUS by writing 0

[patchbot@xxxxxxx]

commit 6fd56bc825e633470fb0807785cd32dbee8182a6
Author:     Haozhong Zhang <haozhong.zhang@xxxxxxxxx>
AuthorDate: Wed Mar 8 15:10:45 2017 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Wed Mar 8 15:10:45 2017 +0100

    x86/mce: clear MSR_IA32_MCG_STATUS by writing 0
    
    On Intel CPU, an attemp to write to MSR_IA32_MCG_STATUS with any
    non-zero value would result in #GP.
    
    This commit writes 0 on AMD CPU as well instead of just clearing MCIP
    bit, because all non-reserved bits of MSR_IA32_MCG_STATUS have been
    handled at this point.
    
    Signed-off-by: Haozhong Zhang <haozhong.zhang@xxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
    Reviewed-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>
---
 xen/arch/x86/cpu/mcheck/mce.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c
index c4ffb27..35117f8 100644
--- a/xen/arch/x86/cpu/mcheck/mce.c
+++ b/xen/arch/x86/cpu/mcheck/mce.c
@@ -535,7 +535,7 @@ void mcheck_cmn_handler(const struct cpu_user_regs *regs)
     gstatus = mca_rdmsr(MSR_IA32_MCG_STATUS);
     if ((gstatus & MCG_STATUS_MCIP) != 0) {
         mce_printk(MCE_CRITICAL, "MCE: Clear MCIP@ last step");
-        mca_wrmsr(MSR_IA32_MCG_STATUS, gstatus & ~MCG_STATUS_MCIP);
+        mca_wrmsr(MSR_IA32_MCG_STATUS, 0);
     }
     mce_barrier_exit(&mce_trap_bar);
 
--
generated by git-patchbot for /home/xen/git/xen.git#master

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