[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen stable-4.8] xen/arm: flush icache as well when XEN_DOMCTL_cacheflush is issued
commit 07f9ddfc9abe9d25288168dfe3c4b830b416f33b Author: Tamas K Lengyel <tamas.lengyel@xxxxxxxxxxxx> AuthorDate: Fri Jan 27 11:25:23 2017 -0700 Commit: Stefano Stabellini <sstabellini@xxxxxxxxxx> CommitDate: Thu Mar 16 13:56:37 2017 -0700 xen/arm: flush icache as well when XEN_DOMCTL_cacheflush is issued When the toolstack modifies memory of a running ARM VM it may happen that the underlying memory of a current vCPU PC is changed. Without flushing the icache the vCPU may continue executing stale instructions. Also expose the xc_domain_cacheflush through xenctrl.h. Signed-off-by: Tamas K Lengyel <tamas.lengyel@xxxxxxxxxxxx> Acked-by: Wei Liu <wei.liu2@xxxxxxxxxx> Reviewed-by: Stefano Stabellini <sstabellini@xxxxxxxxxx> --- tools/libxc/include/xenctrl.h | 8 ++++++++ tools/libxc/xc_domain.c | 6 +++--- tools/libxc/xc_private.h | 3 --- xen/arch/arm/mm.c | 10 ++++++++++ 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h index 2c83544..a71e98e 100644 --- a/tools/libxc/include/xenctrl.h +++ b/tools/libxc/include/xenctrl.h @@ -2710,6 +2710,14 @@ int xc_livepatch_revert(xc_interface *xch, char *name, uint32_t timeout); int xc_livepatch_unload(xc_interface *xch, char *name, uint32_t timeout); int xc_livepatch_replace(xc_interface *xch, char *name, uint32_t timeout); +/* + * Ensure cache coherency after memory modifications. A call to this function + * is only required on ARM as the x86 architecture provides cache coherency + * guarantees. Calling this function on x86 is allowed but has no effect. + */ +int xc_domain_cacheflush(xc_interface *xch, uint32_t domid, + xen_pfn_t start_pfn, xen_pfn_t nr_pfns); + /* Compat shims */ #include "xenctrl_compat.h" diff --git a/tools/libxc/xc_domain.c b/tools/libxc/xc_domain.c index 296b852..98ab6ba 100644 --- a/tools/libxc/xc_domain.c +++ b/tools/libxc/xc_domain.c @@ -74,10 +74,10 @@ int xc_domain_cacheflush(xc_interface *xch, uint32_t domid, /* * The x86 architecture provides cache coherency guarantees which prevent * the need for this hypercall. Avoid the overhead of making a hypercall - * just for Xen to return -ENOSYS. + * just for Xen to return -ENOSYS. It is safe to ignore this call on x86 + * so we just return 0. */ - errno = ENOSYS; - return -1; + return 0; #else DECLARE_DOMCTL; domctl.cmd = XEN_DOMCTL_cacheflush; diff --git a/tools/libxc/xc_private.h b/tools/libxc/xc_private.h index 97445ae..fddebdc 100644 --- a/tools/libxc/xc_private.h +++ b/tools/libxc/xc_private.h @@ -366,9 +366,6 @@ void bitmap_byte_to_64(uint64_t *lp, const uint8_t *bp, int nbits); /* Optionally flush file to disk and discard page cache */ void discard_file_cache(xc_interface *xch, int fd, int flush); -int xc_domain_cacheflush(xc_interface *xch, uint32_t domid, - xen_pfn_t start_pfn, xen_pfn_t nr_pfns); - #define MAX_MMU_UPDATES 1024 struct xc_mmu { mmu_update_t updates[MAX_MMU_UPDATES]; diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 99588a3..596283f 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -390,6 +390,16 @@ void flush_page_to_ram(unsigned long mfn) clean_and_invalidate_dcache_va_range(v, PAGE_SIZE); unmap_domain_page(v); + + /* + * For some of the instruction cache (such as VIPT), the entire I-Cache + * needs to be flushed to guarantee that all the aliases of a given + * physical address will be removed from the cache. + * Invalidating the I-Cache by VA highly depends on the behavior of the + * I-Cache (See D4.9.2 in ARM DDI 0487A.k_iss10775). Instead of using flush + * by VA on select platforms, we just flush the entire cache here. + */ + invalidate_icache(); } void __init arch_init_memory(void) -- generated by git-patchbot for /home/xen/git/xen.git#stable-4.8 _______________________________________________ Xen-changelog mailing list Xen-changelog@xxxxxxxxxxxxx https://lists.xenproject.org/xen-changelog
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