[Xen-changelog] [xen stable-4.8] x86/vpmu_intel: fix hypervisor crash by masking PC bit in MSR_P6_EVNTSEL

[patchbot@xxxxxxx]

commit 98cefccaee180b36754bd4872d07d7e8991ce93d
Author:     Mohit Gambhir <mohit.gambhir@xxxxxxxxxx>
AuthorDate: Fri Jun 9 13:35:00 2017 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Fri Jun 9 13:35:00 2017 +0200

    x86/vpmu_intel: fix hypervisor crash by masking PC bit in MSR_P6_EVNTSEL
    
    Setting Pin Control (PC) bit (19) in MSR_P6_EVNTSEL results in a General
    Protection Fault and thus results in a hypervisor crash. This behavior has
    been observed on two generations of Intel processors namely, Haswell and
    Broadwell. Other Intel processor generations were not tested. However, it
    does seem to be a possible erratum that hasn't yet been confirmed by Intel.
    
    To fix the problem this patch masks PC bit and returns an error in
    case any guest tries to write to it on any Intel processor. In addition
    to the fact that setting this bit crashes the hypervisor on Haswell and
    Broadwell, the PC flag bit toggles a hardware pin on the physical CPU
    every time the programmed event occurs and the hardware behavior in
    response to the toggle is undefined in the SDM, which makes this bit
    unsafe to be used by guests and hence should be masked on all machines.
    
    Signed-off-by: Mohit Gambhir <mohit.gambhir@xxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
    Acked-by: Kevin Tian <kevin.tian@xxxxxxxxx>
    master commit: 8bf68dca65e2d61f4dfc6715cca51ad3dd5aadf1
    master date: 2017-05-08 13:37:17 +0200
---
 xen/arch/x86/cpu/vpmu_intel.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c
index 613aafe..7f9add1 100644
--- a/xen/arch/x86/cpu/vpmu_intel.c
+++ b/xen/arch/x86/cpu/vpmu_intel.c
@@ -80,12 +80,13 @@ static bool_t __read_mostly full_width_write;
 #define FIXED_CTR_CTRL_MASK ((1 << FIXED_CTR_CTRL_BITS) - 1)
 
 #define ARCH_CNTR_ENABLED   (1ULL << 22)
+#define ARCH_CNTR_PIN_CONTROL (1ULL << 19)
 
 /* Number of general-purpose and fixed performance counters */
 static unsigned int __read_mostly arch_pmc_cnt, fixed_pmc_cnt;
 
 /* Masks used for testing whether and MSR is valid */
-#define ARCH_CTRL_MASK  (~((1ull << 32) - 1) | (1ull << 21))
+#define ARCH_CTRL_MASK  (~((1ull << 32) - 1) | (1ull << 21) | 
ARCH_CNTR_PIN_CONTROL)
 static uint64_t __read_mostly fixed_ctrl_mask, fixed_counters_mask;
 static uint64_t __read_mostly global_ovf_ctrl_mask, global_ctrl_mask;
 
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.8

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