[Xen-changelog] [xen stable-4.6] xen/arm: flush icache as well when XEN_DOMCTL_cacheflush is issued

[patchbot@xxxxxxx]

commit 9e469a5f8ec7b2c63c0eb067ce7d5f74974d2d58
Author:     Stefano Stabellini <sstabellini@xxxxxxxxxx>
AuthorDate: Mon Jun 12 14:17:38 2017 -0700
Commit:     Stefano Stabellini <sstabellini@xxxxxxxxxx>
CommitDate: Mon Jun 12 14:17:38 2017 -0700

    xen/arm: flush icache as well when XEN_DOMCTL_cacheflush is issued
    
    When the toolstack modifies memory of a running ARM VM it may happen
    that the underlying memory of a current vCPU PC is changed. Without
    flushing the icache the vCPU may continue executing stale instructions.
    
    Also expose the xc_domain_cacheflush through xenctrl.h.
    
    Signed-off-by: Tamas K Lengyel <tamas.lengyel@xxxxxxxxxxxx>
    Acked-by: Wei Liu <wei.liu2@xxxxxxxxxx>
    Reviewed-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>
    master-commit-id: fe6e8188f3ad91e166338b9962a06afab9b776cd
---
 tools/libxc/include/xenctrl.h |  8 ++++++++
 tools/libxc/xc_domain.c       |  6 +++---
 tools/libxc/xc_private.h      |  3 ---
 xen/arch/arm/mm.c             | 10 ++++++++++
 4 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index 37205c2..f5dbc8b 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2841,6 +2841,14 @@ int xc_psr_cat_get_l3_info(xc_interface *xch, uint32_t 
socket,
                            uint32_t *cos_max, uint32_t *cbm_len);
 #endif
 
+/*
+ * Ensure cache coherency after memory modifications. A call to this function
+ * is only required on ARM as the x86 architecture provides cache coherency
+ * guarantees. Calling this function on x86 is allowed but has no effect.
+ */
+int xc_domain_cacheflush(xc_interface *xch, uint32_t domid,
+                         xen_pfn_t start_pfn, xen_pfn_t nr_pfns);
+
 #endif /* XENCTRL_H */
 
 /*
diff --git a/tools/libxc/xc_domain.c b/tools/libxc/xc_domain.c
index 09ef748..c0eeed2 100644
--- a/tools/libxc/xc_domain.c
+++ b/tools/libxc/xc_domain.c
@@ -83,10 +83,10 @@ int xc_domain_cacheflush(xc_interface *xch, uint32_t domid,
     /*
      * The x86 architecture provides cache coherency guarantees which prevent
      * the need for this hypercall.  Avoid the overhead of making a hypercall
-     * just for Xen to return -ENOSYS.
+     * just for Xen to return -ENOSYS.  It is safe to ignore this call on x86
+     * so we just return 0.
      */
-    errno = ENOSYS;
-    return -1;
+    return 0;
 #else
     DECLARE_DOMCTL;
     domctl.cmd = XEN_DOMCTL_cacheflush;
diff --git a/tools/libxc/xc_private.h b/tools/libxc/xc_private.h
index 2df1d59..1ee6a77 100644
--- a/tools/libxc/xc_private.h
+++ b/tools/libxc/xc_private.h
@@ -389,9 +389,6 @@ void bitmap_byte_to_64(uint64_t *lp, const uint8_t *bp, int 
nbits);
 /* Optionally flush file to disk and discard page cache */
 void discard_file_cache(xc_interface *xch, int fd, int flush);
 
-int xc_domain_cacheflush(xc_interface *xch, uint32_t domid,
-                        xen_pfn_t start_pfn, xen_pfn_t nr_pfns);
-
 #define MAX_MMU_UPDATES 1024
 struct xc_mmu {
     mmu_update_t updates[MAX_MMU_UPDATES];
diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index 27b9fc4..6334d40 100644
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -390,6 +390,16 @@ void flush_page_to_ram(unsigned long mfn)
 
     clean_and_invalidate_dcache_va_range(v, PAGE_SIZE);
     unmap_domain_page(v);
+
+    /*
+     * For some of the instruction cache (such as VIPT), the entire I-Cache
+     * needs to be flushed to guarantee that all the aliases of a given
+     * physical address will be removed from the cache.
+     * Invalidating the I-Cache by VA highly depends on the behavior of the
+     * I-Cache (See D4.9.2 in ARM DDI 0487A.k_iss10775). Instead of using flush
+     * by VA on select platforms, we just flush the entire cache here.
+     */
+    invalidate_icache();
 }
 
 void __init arch_init_memory(void)
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.6

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