[Xen-changelog] [xen master] arm: processor: add new struct hsr_smc32 into hsr union

[patchbot@xxxxxxx]

commit 830c83af5047db78b973875d8cc7ead8b7aad535
Author:     Volodymyr Babchuk <volodymyr_babchuk@xxxxxxxx>
AuthorDate: Wed Aug 16 21:44:55 2017 +0300
Commit:     Stefano Stabellini <sstabellini@xxxxxxxxxx>
CommitDate: Fri Aug 18 10:27:51 2017 -0700

    arm: processor: add new struct hsr_smc32 into hsr union
    
    On ARMv8, one of conditional exceptions (SMC that originates
    from AArch32 state) has extra field in HSR.ISS encoding:
    
    CCKNOWNPASS, bit [19]
    Indicates whether the instruction might have failed its condition
    code check.
       0 - The instruction was unconditional, or was conditional and
       passed  its condition code check.
       1 - The instruction was conditional, and might have failed its
       condition code check.
    (ARM DDI 0487B.a page D7-2272)
    
    This is an instruction specific field, so better to add new structure
    to union hsr. This structure describes ISS encoding for an exception
    from SMC instruction executing in AArch32 state. But we define this
    struct for both ARMv7 and ARMv8, because ARMv8 encoding is backwards
    compatible with ARMv7.
    
    Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@xxxxxxxx>
    Acked-by: Julien Grall <julien.grall@xxxxxxx>
    Signed-off-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>
---
 xen/include/asm-arm/processor.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index bf0e1bd..9f7a42f 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -549,6 +549,23 @@ union hsr {
         unsigned long ec:6;     /* Exception Class */
     } cp; /* HSR_EC_CP */
 
+    /*
+     * This encoding is valid only for ARMv8 (ARM DDI 0487B.a, pages D7-2271 
and
+     * G6-4957). On ARMv7, encoding ISS for EC=0x13 is defined as UNK/SBZP
+     * (ARM DDI 0406C.c page B3-1431). UNK/SBZP means that hardware implements
+     * this field as Read-As-Zero. ARMv8 is backwards compatible with ARMv7:
+     * reading CCKNOWNPASS on ARMv7 will return 0, which means that condition
+     * check was passed or instruction was unconditional.
+     */
+    struct hsr_smc32 {
+        unsigned long res0:19;  /* Reserved */
+        unsigned long ccknownpass:1; /* Instruction passed conditional check */
+        unsigned long cc:4;    /* Condition Code */
+        unsigned long ccvalid:1;/* CC Valid */
+        unsigned long len:1;   /* Instruction length */
+        unsigned long ec:6;    /* Exception Class */
+    } smc32; /* HSR_EC_SMC32 */
+
 #ifdef CONFIG_ARM_64
     struct hsr_sysreg {
         unsigned long read:1;   /* Direction */
--
generated by git-patchbot for /home/xen/git/xen.git#master

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