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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen stable-4.7] x86: avoid #GP for PV guest MSR accesses
commit 5805ab112bd9d509efcc6aa24c52085c5eb7ef71
Author: Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Tue Oct 24 16:48:50 2017 +0200
Commit: Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Tue Oct 24 16:48:50 2017 +0200
x86: avoid #GP for PV guest MSR accesses
Halfway recent Linux kernels probe MISC_FEATURES_ENABLES on all CPUs,
leading to ugly recovered #GP fault messages with debug builds on older
systems. We can do better, so introduce synthetic feature flags for
both this and PLATFORM_INFO to avoid the rdmsr_safe() altogether.
Note that the r/o nature of PLATFORM_INFO is now also being enforced.
The rdmsr_safe() uses for MISC_ENABLE are left in place as benign - it
exists for all 64-bit capable Intel CPUs (see e.g. early_init_intel()).
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
xen/arch/x86/cpu/intel.c | 10 ++++++++--
xen/arch/x86/traps.c | 10 +++-------
xen/include/asm-x86/cpufeature.h | 1 +
3 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 7b60aaa..181e815 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -22,8 +22,12 @@ static bool_t __init probe_intel_cpuid_faulting(void)
{
uint64_t x;
- if (rdmsr_safe(MSR_INTEL_PLATFORM_INFO, x) ||
- !(x & MSR_PLATFORM_INFO_CPUID_FAULTING))
+ if (rdmsr_safe(MSR_INTEL_PLATFORM_INFO, x))
+ return 0;
+
+ __set_bit(X86_FEATURE_MSR_PLATFORM_INFO, boot_cpu_data.x86_capability);
+
+ if (!(x & MSR_PLATFORM_INFO_CPUID_FAULTING))
return 0;
expected_levelling_cap |= LCAP_faulting;
@@ -321,6 +325,8 @@ static void early_init_intel(struct cpuinfo_x86 *c)
if (test_bit(X86_FEATURE_CPUID_FAULTING, boot_cpu_data.x86_capability))
__set_bit(X86_FEATURE_CPUID_FAULTING, c->x86_capability);
+ if (test_bit(X86_FEATURE_MSR_PLATFORM_INFO,
boot_cpu_data.x86_capability))
+ __set_bit(X86_FEATURE_MSR_PLATFORM_INFO, c->x86_capability);
intel_ctxt_switch_levelling(NULL);
}
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 90b6071..3200850 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2866,11 +2866,8 @@ static int emulate_privileged_op(struct cpu_user_regs
*regs)
break;
case MSR_INTEL_PLATFORM_INFO:
- if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
- msr_content ||
- rdmsr_safe(MSR_INTEL_PLATFORM_INFO, msr_content) )
- goto fail;
- break;
+ /* The MSR is read-only. */
+ goto fail;
case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR(7):
case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL(3):
@@ -3001,8 +2998,7 @@ static int emulate_privileged_op(struct cpu_user_regs
*regs)
break;
case MSR_INTEL_PLATFORM_INFO:
- if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
- rdmsr_safe(MSR_INTEL_PLATFORM_INFO, val) )
+ if ( !boot_cpu_has(X86_FEATURE_MSR_PLATFORM_INFO) )
goto fail;
regs->eax = regs->edx = 0;
break;
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 9c49206..1a11ebe 100644
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -25,6 +25,7 @@
#define X86_FEATURE_CPUID_FAULTING ((FSCAPINTS+0)*32+ 6) /* cpuid faulting
*/
#define X86_FEATURE_CLFLUSH_MONITOR ((FSCAPINTS+0)*32+ 7) /* clflush reqd
with monitor */
#define X86_FEATURE_APERFMPERF ((FSCAPINTS+0)*32+ 8) /* APERFMPERF */
+#define X86_FEATURE_MSR_PLATFORM_INFO ((FSCAPINTS+0)*32+ 9) /* PLATFORM_INFO
MSR present */
#define cpufeat_word(idx) ((idx) / 32)
#define cpufeat_bit(idx) ((idx) % 32)
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.7
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