[Xen-changelog] [xen master] arm: configure interrupts to be in non-secure group1

[patchbot@xxxxxxx]

commit 0c8055c2f45f489aff67f4d362f3fdc192cc2d94
Author:     Stefano Stabellini <sstabellini@xxxxxxxxxx>
AuthorDate: Wed Oct 18 14:29:58 2017 -0700
Commit:     Stefano Stabellini <sstabellini@xxxxxxxxxx>
CommitDate: Thu Oct 19 13:31:43 2017 -0700

    arm: configure interrupts to be in non-secure group1
    
    Xen uses non-secure group1 interrupts, however it doesn't configure the
    GICv3 accordingly. Xen needs to set GICD_IGROUPR for SPIs and
    GICR_IGROUPR0 for local interrupt to "1" to specify that interrupts
    belong to group1. This is particularly important if the system has
    GICD_CTLR.DS set, also see commit
    7c9b973061b03af62734f613f6abec46c0dd4a88 in Linux.
    
    Signed-off-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>
    Reviewed-by: Julien Grall <julien.grall@xxxxxxxxxx>
    Released-acked-by: Julien Grall <julien.grall@xxxxxxxxxx>
---
 xen/arch/arm/gic-v3.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 74d00e0..3c04d4a 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -569,6 +569,13 @@ static void __init gicv3_dist_init(void)
     for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i += 32 )
         writel_relaxed(0xffffffff, GICD + GICD_ICENABLER + (i / 32) * 4);
 
+    /*
+     * Configure SPIs as non-secure Group-1. This will only matter
+     * if the GIC only has a single security state.
+     */
+    for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i += 32 )
+        writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * 4);
+
     gicv3_dist_wait_for_rwp();
 
     /* Turn on the distributor */
@@ -775,6 +782,8 @@ static int gicv3_cpu_init(void)
      */
     writel_relaxed(0xffff0000, GICD_RDIST_SGI_BASE + GICR_ICENABLER0);
     writel_relaxed(0x0000ffff, GICD_RDIST_SGI_BASE + GICR_ISENABLER0);
+    /* Configure SGIs/PPIs as non-secure Group-1 */
+    writel_relaxed(GENMASK(31, 0), GICD_RDIST_SGI_BASE + GICR_IGROUPR0);
 
     gicv3_redist_wait_for_rwp();
 
--
generated by git-patchbot for /home/xen/git/xen.git#master

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