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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen stable-4.7] x86/feature: Definitions for Indirect Branch Controls
commit f9616884e16b8028c257c8b01fb12daff7fe3454
Author: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Wed Feb 14 11:34:14 2018 +0100
Commit: Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Wed Feb 14 11:34:14 2018 +0100
x86/feature: Definitions for Indirect Branch Controls
Contemporary processors are gaining Indirect Branch Controls via microcode
updates. Intel are introducing one bit to indicate IBRS and IBPB support,
and
a second bit for STIBP. AMD are introducing IBPB only, so enumerate it
with a
separate bit.
Furthermore, depending on compiler and microcode availability, we may want
to
run Xen with IBRS set, or clear.
To use these facilities, we synthesise separate IBRS and IBPB bits for
internal use. A lot of infrastructure is required before these features are
safe to offer to guests.
This is part of XSA-254.
Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
Acked-by: Wei Liu <wei.liu2@xxxxxxxxxx>
master commit: 0d703a701cc4bc47773986b2796eebd28b1439b5
master date: 2018-01-16 17:45:50 +0000
---
tools/libxc/xc_cpuid_x86.c | 8 ++++++--
tools/libxl/libxl_cpuid.c | 3 +++
tools/misc/xen-cpuid.c | 16 +++++++++++++++-
xen/arch/x86/cpu/common.c | 2 +-
xen/arch/x86/spec_ctrl.c | 17 +++++++++++++++++
xen/include/asm-x86/cpufeature.h | 3 +++
xen/include/asm-x86/msr-index.h | 8 ++++++++
xen/include/public/arch-x86/cpufeatureset.h | 5 +++++
xen/tools/gen-cpuid.py | 5 +++++
9 files changed, 63 insertions(+), 4 deletions(-)
diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
index fbbac9e..4d30b47 100644
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -540,13 +540,15 @@ static void xc_cpuid_hvm_policy(xc_interface *xch,
{
regs[1] = info->featureset[featureword_of(X86_FEATURE_FSGSBASE)];
regs[2] =
info->featureset[featureword_of(X86_FEATURE_PREFETCHWT1)];
+ regs[3] = info->featureset[featureword_of(X86_FEATURE_IBRSB)];
}
else
{
regs[1] = 0;
regs[2] = 0;
+ regs[3] = 0;
}
- regs[0] = regs[3] = 0;
+ regs[0] = 0;
break;
case 0x0000000d:
@@ -625,13 +627,15 @@ static void xc_cpuid_pv_policy(xc_interface *xch,
{
regs[1] = info->featureset[featureword_of(X86_FEATURE_FSGSBASE)];
regs[2] =
info->featureset[featureword_of(X86_FEATURE_PREFETCHWT1)];
+ regs[3] = info->featureset[featureword_of(X86_FEATURE_IBRSB)];
}
else
{
regs[1] = 0;
regs[2] = 0;
+ regs[3] = 0;
}
- regs[0] = regs[3] = 0;
+ regs[0] = 0;
break;
case 0x0000000d:
diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c
index fc20157..279b3c3 100644
--- a/tools/libxl/libxl_cpuid.c
+++ b/tools/libxl/libxl_cpuid.c
@@ -158,6 +158,8 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list
*cpuid, const char* str)
{"de", 0x00000001, NA, CPUID_REG_EDX, 2, 1},
{"vme", 0x00000001, NA, CPUID_REG_EDX, 1, 1},
{"fpu", 0x00000001, NA, CPUID_REG_EDX, 0, 1},
+ {"ibrsb", 0x00000007, 0, CPUID_REG_EDX, 26, 1},
+ {"stibp", 0x00000007, 0, CPUID_REG_EDX, 27, 1},
{"topoext", 0x80000001, NA, CPUID_REG_ECX, 22, 1},
{"tbm", 0x80000001, NA, CPUID_REG_ECX, 21, 1},
{"nodeid", 0x80000001, NA, CPUID_REG_ECX, 19, 1},
@@ -187,6 +189,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list
*cpuid, const char* str)
{"nx", 0x80000001, NA, CPUID_REG_EDX, 20, 1},
{"syscall", 0x80000001, NA, CPUID_REG_EDX, 11, 1},
{"procpkg", 0x00000004, 0, CPUID_REG_EAX, 26, 6},
+ {"ibpb", 0x80000008, NA, CPUID_REG_EBX, 12, 1},
{"apicidsize", 0x80000008, NA, CPUID_REG_ECX, 12, 4},
{"nc", 0x80000008, NA, CPUID_REG_ECX, 0, 8},
{"svm_npt", 0x8000000a, NA, CPUID_REG_EDX, 0, 1},
diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
index 44991f6..0981366 100644
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -140,7 +140,20 @@ static const char *str_e8b[32] =
{
[ 0] = "clzero",
- [1 ... 31] = "REZ",
+ [1 ... 11] = "REZ",
+
+ [12] = "ibpb",
+
+ [13 ... 31] = "REZ",
+};
+
+static const char *str_7d0[32] =
+{
+ [0 ... 25] = "REZ",
+
+ [26] = "ibrsb", [27] = "stibp",
+
+ [28 ... 31] = "REZ",
};
static struct {
@@ -158,6 +171,7 @@ static struct {
{ "0x00000007:0.ecx", "7c0", str_7c0 },
{ "0x80000007.edx", "e7d", str_e7d },
{ "0x80000008.ebx", "e8b", str_e8b },
+ { "0x00000007:0.edx", "7d0", str_7d0 },
};
#define COL_ALIGN "18"
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 35f0ba1..48f3aa5 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -321,7 +321,7 @@ static void generic_identify(struct cpuinfo_x86 *c)
cpuid_count(0x00000007, 0, &tmp,
&c->x86_capability[cpufeat_word(X86_FEATURE_FSGSBASE)],
&c->x86_capability[cpufeat_word(X86_FEATURE_PKU)],
- &tmp);
+
&c->x86_capability[cpufeat_word(X86_FEATURE_IBRSB)]);
}
/*
diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 77257ee..68a485a 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -67,8 +67,25 @@ custom_param("bti", parse_bti);
static void __init print_details(enum ind_thunk thunk)
{
+ unsigned int _7d0 = 0, e8b = 0, tmp;
+
+ /* Collect diagnostics about available mitigations. */
+ if ( boot_cpu_data.cpuid_level >= 7 )
+ cpuid_count(7, 0, &tmp, &tmp, &tmp, &_7d0);
+ if ( boot_cpu_data.extended_cpuid_level >= 0x80000008 )
+ cpuid(0x80000008, &tmp, &e8b, &tmp, &tmp);
+
printk(XENLOG_DEBUG "Speculative mitigation facilities:\n");
+ /* Hardware features which pertain to speculative mitigations. */
+ if ( (_7d0 & (cpufeat_mask(X86_FEATURE_IBRSB) |
+ cpufeat_mask(X86_FEATURE_STIBP))) ||
+ (e8b & cpufeat_mask(X86_FEATURE_IBPB)) )
+ printk(XENLOG_DEBUG " Hardware features:%s%s%s\n",
+ (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB)) ? " IBRS/IBPB" : "",
+ (_7d0 & cpufeat_mask(X86_FEATURE_STIBP)) ? " STIBP" : "",
+ (e8b & cpufeat_mask(X86_FEATURE_IBPB)) ? " IBPB" : "");
+
/* Compiled-in support which pertains to BTI mitigations. */
if ( IS_ENABLED(CONFIG_INDIRECT_THUNK) )
printk(XENLOG_DEBUG " Compiled-in support: INDIRECT_THUNK\n");
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 3dc56e7..bacfbfc 100644
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -29,6 +29,9 @@
#define X86_FEATURE_LFENCE_DISPATCH ((FSCAPINTS+0)*32+ 10) /* lfence set as
Dispatch Serialising */
#define X86_FEATURE_IND_THUNK_LFENCE ((FSCAPINTS+0)*32+ 11) /* Use
IND_THUNK_LFENCE */
#define X86_FEATURE_IND_THUNK_JMP ((FSCAPINTS+0)*32+ 12) /* Use
IND_THUNK_JMP */
+#define X86_FEATURE_XEN_IBPB ((FSCAPINTS+0)*32+ 13) /* IBRSB || IBPB
*/
+#define X86_FEATURE_XEN_IBRS_SET ((FSCAPINTS+0)*32+ 14) /* IBRSB && IRBS
set in Xen */
+#define X86_FEATURE_XEN_IBRS_CLEAR ((FSCAPINTS+0)*32+ 15) /* IBRSB && IBRS
clear in Xen */
#define cpufeat_word(idx) ((idx) / 32)
#define cpufeat_bit(idx) ((idx) % 32)
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 21cd662..96d3eb0 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -31,6 +31,14 @@
#define EFER_LMSLE (1<<_EFER_LMSLE)
#define EFER_FFXSE (1<<_EFER_FFXSE)
+/* Speculation Controls. */
+#define MSR_SPEC_CTRL 0x00000048
+#define SPEC_CTRL_IBRS (_AC(1, ULL) << 0)
+#define SPEC_CTRL_STIBP (_AC(1, ULL) << 1)
+
+#define MSR_PRED_CMD 0x00000049
+#define PRED_CMD_IBPB (_AC(1, ULL) << 0)
+
/* Intel MSRs. Some also available on other CPUs */
#define MSR_IA32_PERFCTR0 0x000000c1
#define MSR_IA32_A_PERFCTR0 0x000004c1
diff --git a/xen/include/public/arch-x86/cpufeatureset.h
b/xen/include/public/arch-x86/cpufeatureset.h
index 39acf8c..4f8cef2 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -224,6 +224,11 @@ XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF
Read Only interface */
/* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */
XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */
+XEN_CPUFEATURE(IBPB, 8*32+12) /* IBPB support only (no IBRS, used
by AMD) */
+
+/* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */
+XEN_CPUFEATURE(IBRSB, 9*32+26) /* IBRS and IBPB support (used by
Intel) */
+XEN_CPUFEATURE(STIBP, 9*32+27) /* STIBP */
#endif /* XEN_CPUFEATURE */
diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
index 7135fd2..ad8b632 100755
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -244,6 +244,11 @@ def crunch_numbers(state):
# AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the
# standard 3DNow in the earlier K6 processors.
_3DNOW: [_3DNOWEXT],
+
+ # Single Thread Indirect Branch Predictors enumerates a new bit in the
+ # MSR enumerated by Indirect Branch Restricted Speculation/Indirect
+ # Branch Prediction Barrier enumeration.
+ IBRSB: [STIBP],
}
deep_features = tuple(sorted(deps.keys()))
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.7
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