[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen stable-4.7] x86/entry: Use 32bit xors rater than 64bit xors for clearing GPRs
commit ad52760b9bd89929fdc04402c84d8a1df072a8e0 Author: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> AuthorDate: Tue Mar 6 16:20:48 2018 +0100 Commit: Jan Beulich <jbeulich@xxxxxxxx> CommitDate: Tue Mar 6 16:20:48 2018 +0100 x86/entry: Use 32bit xors rater than 64bit xors for clearing GPRs Intel's Silvermont/Knights Landing architecture treats them as full ALU operations, rather than zeroing idoms. No functional change, and no change in code volume (only changing the bit selection in the REX prefix). Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> Acked-by: Jan Beulich <jbeulich@xxxxxxxx> master commit: eb1d3a3f04b85d596862a4c9dcf796e67ab4dc09 master date: 2018-02-15 11:08:27 +0000 --- xen/include/asm-x86/asm_defns.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/xen/include/asm-x86/asm_defns.h b/xen/include/asm-x86/asm_defns.h index 0749b8f5fa..b01ba0e64c 100644 --- a/xen/include/asm-x86/asm_defns.h +++ b/xen/include/asm-x86/asm_defns.h @@ -271,10 +271,10 @@ static always_inline void stac(void) movq %r10,UREGS_r10(%rsp) movq %r11,UREGS_r11(%rsp) .endif - xor %r8, %r8 - xor %r9, %r9 - xor %r10, %r10 - xor %r11, %r11 + xor %r8d, %r8d + xor %r9d, %r9d + xor %r10d, %r10d + xor %r11d, %r11d movq %rbx,UREGS_rbx(%rsp) xor %ebx, %ebx movq %rbp,UREGS_rbp(%rsp) @@ -291,10 +291,10 @@ static always_inline void stac(void) movq %r14,UREGS_r14(%rsp) movq %r15,UREGS_r15(%rsp) .endif - xor %r12, %r12 - xor %r13, %r13 - xor %r14, %r14 - xor %r15, %r15 + xor %r12d, %r12d + xor %r13d, %r13d + xor %r14d, %r14d + xor %r15d, %r15d .endm #define LOAD_ONE_REG(reg, compat) \ -- generated by git-patchbot for /home/xen/git/xen.git#stable-4.7 _______________________________________________ Xen-changelog mailing list Xen-changelog@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/xen-changelog
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