[Xen-changelog] [xen stable-4.8] x86: ignore guest microcode loading attempts

[patchbot@xxxxxxx]

commit ce185fbce2912702eef295afb31dc4ba163c06b6
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Fri Mar 16 17:19:20 2018 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Fri Mar 16 17:19:20 2018 +0100

    x86: ignore guest microcode loading attempts
    
    The respective MSRs are write-only, and hence attempts by guests to
    write to these are - as of 1f1d183d49 ("x86/HVM: don't give the wrong
    impression of WRMSR succeeding") no longer ignored. Restore original
    behavior for the two affected MSRs.
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    master commit: 59c0983e10d70ea2368085271b75fb007811fe52
    master date: 2018-03-15 12:44:24 +0100
---
 xen/arch/x86/hvm/hvm.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 2e6775ba5d..96afb7b1c2 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -3927,6 +3927,8 @@ int hvm_msr_read_intercept(unsigned int msr, uint64_t 
*msr_content)
             goto gp_fault;
         break;
 
+    case MSR_AMD_PATCHLOADER:
+    case MSR_IA32_UCODE_WRITE:
     case MSR_PRED_CMD:
         /* Write-only */
         goto gp_fault;
@@ -4092,6 +4094,26 @@ int hvm_msr_write_intercept(unsigned int msr, uint64_t 
msr_content,
             goto gp_fault;
         break;
 
+    case MSR_AMD_PATCHLOADER:
+        /*
+         * See note on MSR_IA32_UCODE_WRITE below, which may or may not apply
+         * to AMD CPUs as well (at least the architectural/CPUID part does).
+         */
+        if ( v->domain->arch.x86_vendor != X86_VENDOR_AMD )
+            goto gp_fault;
+        break;
+
+    case MSR_IA32_UCODE_WRITE:
+        /*
+         * Some versions of Windows at least on certain hardware try to load
+         * microcode before setting up an IDT. Therefore we must not inject #GP
+         * for such attempts. Also the MSR is architectural and not qualified
+         * by any CPUID bit.
+         */
+        if ( v->domain->arch.x86_vendor != X86_VENDOR_INTEL )
+            goto gp_fault;
+        break;
+
     case MSR_IA32_XSS:
         ecx = 1;
         hvm_cpuid(XSTATE_CPUID, &eax, NULL, &ecx, NULL);
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.8

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