[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Xen-changelog] [xen stable-4.10] xen/arm: Relax ARM_SMCCC_ARCH_WORKAROUND_1 discovery

commit 2e34343fb2c8b62e8e98b21a569beea508f501f6
Author:     Julien Grall <julien.grall@xxxxxxx>
AuthorDate: Mon Mar 12 13:19:35 2018 +0000
Commit:     Stefano Stabellini <sstabellini@xxxxxxxxxx>
CommitDate: Wed Apr 4 13:55:15 2018 -0700

    xen/arm: Relax ARM_SMCCC_ARCH_WORKAROUND_1 discovery
    A recent update to the ARM SMCCC_ARCH_WORKAROUND_1 specification (see [1])
    allows firmware to return a non zero, positive value, to describe that
    although the mitigation is implemented at the higher exception level,
    the CPU on which the call is made is not affected.
    Relax the check on the return value from ARM_WORKAROUND_1 so that we
    only error out if the returned value is negative.
    [1] https://developer.arm.com/support/security-update/downloads
    "Firmware interfaces for mitigating CVE-2017-5715 System Software on Arm
    Signed-off-by: Julien Grall <julien.grall@xxxxxxx>
    Reviewed-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>
    (cherry picked from commit 6b270fae7ad462687550a875f714bff18d764416)
 xen/arch/arm/cpuerrata.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c
index 4eb1567589..1baa20654b 100644
--- a/xen/arch/arm/cpuerrata.c
+++ b/xen/arch/arm/cpuerrata.c
@@ -168,7 +168,8 @@ static int enable_smccc_arch_workaround_1(void *data)
                       ARM_SMCCC_ARCH_WORKAROUND_1_FID, &res);
-    if ( res.a0 != ARM_SMCCC_SUCCESS )
+    /* The return value is in the lower 32-bits. */
+    if ( (int)res.a0 < 0 )
         goto warn;
     return !install_bp_hardening_vec(entry,__smccc_workaround_1_smc_start,
generated by git-patchbot for /home/xen/git/xen.git#stable-4.10

Xen-changelog mailing list



Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.