[Xen-changelog] [xen master] ARM: vPL011: Use the VGIC's level triggered IRQs handling if available

[patchbot@xxxxxxx]

commit 31286f7a38d65ee461f88282ffacb1de00238a49
Author:     Andre Przywara <andre.przywara@xxxxxxxxxx>
AuthorDate: Mon Dec 18 17:34:24 2017 +0000
Commit:     Stefano Stabellini <sstabellini@xxxxxxxxxx>
CommitDate: Tue Mar 27 12:44:32 2018 -0700

    ARM: vPL011: Use the VGIC's level triggered IRQs handling if available
    
    The emulated ARM SBSA UART is using level triggered IRQ semantics,
    however the current VGIC can only handle edge triggered IRQs, really.
    Disable the existing workaround for this problem in case we have the
    new VGIC in place, which can properly handle level triggered IRQs.
    
    Signed-off-by: Andre Przywara <andre.przywara@xxxxxxxxxx>
    Reviewed-by: Julien Grall <julien.grall@xxxxxxx>
    Acked-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>
---
 xen/arch/arm/vpl011.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/xen/arch/arm/vpl011.c b/xen/arch/arm/vpl011.c
index 5dcf4bec18..a281eabd7e 100644
--- a/xen/arch/arm/vpl011.c
+++ b/xen/arch/arm/vpl011.c
@@ -54,6 +54,7 @@ static void vpl011_update_interrupt_status(struct domain *d)
      */
     ASSERT(spin_is_locked(&vpl011->lock));
 
+#ifndef CONFIG_NEW_VGIC
     /*
      * TODO: PL011 interrupts are level triggered which means
      * that interrupt needs to be set/clear instead of being
@@ -71,6 +72,9 @@ static void vpl011_update_interrupt_status(struct domain *d)
         vgic_inject_irq(d, NULL, GUEST_VPL011_SPI, true);
 
     vpl011->shadow_uartmis = uartmis;
+#else
+    vgic_inject_irq(d, NULL, GUEST_VPL011_SPI, uartmis);
+#endif
 }
 
 static uint8_t vpl011_read_data(struct domain *d)
--
generated by git-patchbot for /home/xen/git/xen.git#master

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