[Xen-changelog] [xen master] x86/msr: further correct the emulation behaviour of MSR_PRED_CMD

[patchbot@xxxxxxx]

commit a996273d1fc10d14598985703227bfa35a91f681
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Wed Apr 18 11:16:37 2018 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Wed Apr 18 11:16:37 2018 +0200

    x86/msr: further correct the emulation behaviour of MSR_PRED_CMD
    
    Following commit a6aa678fa3 ("x86/msr: Correct the emulation behaviour
    of MSR_PRED_CMD") we may end up writing the low bit with the wrong
    value. While it's unlikely for a guest to want to write zero there, we
    should still permit (this without incurring the overhead of an actual
    barrier). Correcting this right away will also help whenever further
    bits in the MSR might become defined.
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Release-acked-by: Juergen Gross <jgross@xxxxxxxx>
---
 xen/arch/x86/msr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index d0345611c1..da9aa596b1 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -247,7 +247,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
             goto gp_fault; /* Rsvd bit set? */
 
         if ( v == curr )
-            wrmsrl(MSR_PRED_CMD, PRED_CMD_IBPB);
+            wrmsrl(MSR_PRED_CMD, val);
         break;
 
     case MSR_INTEL_MISC_FEATURES_ENABLES:
--
generated by git-patchbot for /home/xen/git/xen.git#master

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