[Xen-changelog] [xen staging-4.10] x86/msr: Virtualise MSR_SPEC_CTRL.SSBD for guests to use

[patchbot@xxxxxxx]

commit c2b84e7cc4dca6ddeb163235cc8a7c654b8ae47a
Author:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Fri Apr 13 15:42:34 2018 +0000
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Tue May 29 09:25:02 2018 +0200

    x86/msr: Virtualise MSR_SPEC_CTRL.SSBD for guests to use
    
    Almost all infrastructure is already in place.  Update the reserved bits
    calculation in guest_wrmsr(), and offer SSBD to guests by default.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/msr.c                          | 8 ++++++--
 xen/include/public/arch-x86/cpufeatureset.h | 2 +-
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index 48d061d7da..21219c4a15 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -178,6 +178,8 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
 
     switch ( msr )
     {
+        uint64_t rsvd;
+
     case MSR_INTEL_PLATFORM_INFO:
     case MSR_ARCH_CAPABILITIES:
         /* Read-only */
@@ -213,8 +215,10 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
          * Note: SPEC_CTRL_STIBP is specified as safe to use (i.e. ignored)
          * when STIBP isn't enumerated in hardware.
          */
+        rsvd = ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP |
+                 (cp->feat.ssbd ? SPEC_CTRL_SSBD : 0));
 
-        if ( val & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP) )
+        if ( val & rsvd )
             goto gp_fault; /* Rsvd bit set? */
 
         vp->spec_ctrl.raw = val;
@@ -233,12 +237,12 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t 
val)
 
     case MSR_INTEL_MISC_FEATURES_ENABLES:
     {
-        uint64_t rsvd = ~0ull;
         bool old_cpuid_faulting = vp->misc_features_enables.cpuid_faulting;
 
         if ( !vp->misc_features_enables.available )
             goto gp_fault;
 
+        rsvd = ~0ull;
         if ( dp->plaform_info.cpuid_faulting )
             rsvd &= ~MSR_MISC_FEATURES_CPUID_FAULTING;
 
diff --git a/xen/include/public/arch-x86/cpufeatureset.h 
b/xen/include/public/arch-x86/cpufeatureset.h
index 7acf8222ac..c721c125ab 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -245,7 +245,7 @@ XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A  AVX512 Multiply 
Accumulation Single
 XEN_CPUFEATURE(IBRSB,         9*32+26) /*A  IBRS and IBPB support (used by 
Intel) */
 XEN_CPUFEATURE(STIBP,         9*32+27) /*A! STIBP */
 XEN_CPUFEATURE(ARCH_CAPS,     9*32+29) /*   IA32_ARCH_CAPABILITIES MSR */
-XEN_CPUFEATURE(SSBD,          9*32+31) /*   MSR_SPEC_CTRL.SSBD available */
+XEN_CPUFEATURE(SSBD,          9*32+31) /*A  MSR_SPEC_CTRL.SSBD available */
 
 #endif /* XEN_CPUFEATURE */
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.10

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