[Xen-changelog] [xen staging-4.9] x86/msr: Virtualise MSR_SPEC_CTRL.SSBD for guests to use

[patchbot@xxxxxxx]

commit 11eb72e820fbe077fb5fc5c7666b0be01b8f6099
Author:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Fri Apr 13 15:42:34 2018 +0000
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Tue May 29 09:52:46 2018 +0200

    x86/msr: Virtualise MSR_SPEC_CTRL.SSBD for guests to use
    
    Almost all infrastructure is already in place.  Update the reserved bits
    calculation in guest_wrmsr(), and offer SSBD to guests by default.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/domctl.c                       | 3 ++-
 xen/arch/x86/hvm/hvm.c                      | 3 ++-
 xen/arch/x86/traps.c                        | 3 ++-
 xen/include/public/arch-x86/cpufeatureset.h | 2 +-
 4 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 187494963e..47b8835c61 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1408,7 +1408,8 @@ long arch_do_domctl(
                      * ignored) when STIBP isn't enumerated in hardware.
                      */
 
-                    if ( msr.value & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP) )
+                    if ( msr.value & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP |
+                                       (d->arch.cpuid->feat.ssbd ? 
SPEC_CTRL_SSBD : 0)) )
                         break;
                     v->arch.spec_ctrl = msr.value;
                     continue;
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 1a47ed98b4..de47c20d0c 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -3619,7 +3619,8 @@ int hvm_msr_write_intercept(unsigned int msr, uint64_t 
msr_content,
          * when STIBP isn't enumerated in hardware.
          */
 
-        if ( msr_content & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP) )
+        if ( msr_content & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP |
+                             (d->arch.cpuid->feat.ssbd ? SPEC_CTRL_SSBD : 0)) )
             goto gp_fault; /* Rsvd bit set? */
 
         v->arch.spec_ctrl = msr_content;
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index b6add03691..93b909c614 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2858,7 +2858,8 @@ static int priv_op_write_msr(unsigned int reg, uint64_t 
val,
          * when STIBP isn't enumerated in hardware.
          */
 
-        if ( val & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP) )
+        if ( val & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP |
+                     (currd->arch.cpuid->feat.ssbd ? SPEC_CTRL_SSBD : 0)) )
             break; /* Rsvd bit set? */
 
         curr->arch.spec_ctrl = val;
diff --git a/xen/include/public/arch-x86/cpufeatureset.h 
b/xen/include/public/arch-x86/cpufeatureset.h
index 43f42b6ddb..f2baea445f 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -244,7 +244,7 @@ XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A  AVX512 Multiply 
Accumulation Single
 XEN_CPUFEATURE(IBRSB,         9*32+26) /*A  IBRS and IBPB support (used by 
Intel) */
 XEN_CPUFEATURE(STIBP,         9*32+27) /*A! STIBP */
 XEN_CPUFEATURE(ARCH_CAPS,     9*32+29) /*   IA32_ARCH_CAPABILITIES MSR */
-XEN_CPUFEATURE(SSBD,          9*32+31) /*   MSR_SPEC_CTRL.SSBD available */
+XEN_CPUFEATURE(SSBD,          9*32+31) /*A  MSR_SPEC_CTRL.SSBD available */
 
 #endif /* XEN_CPUFEATURE */
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.9

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