[Xen-changelog] [xen staging-4.8] x86/msr: Virtualise MSR_SPEC_CTRL.SSBD for guests to use

[patchbot@xxxxxxx]

commit 845d2b63e696d465bbf86a8116d5ad9186db23f0
Author:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Tue May 29 10:11:14 2018 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Tue May 29 10:11:14 2018 +0200

    x86/msr: Virtualise MSR_SPEC_CTRL.SSBD for guests to use
    
    Almost all infrastructure is already in place.  Update the reserved bits
    calculation in guest_wrmsr(), and offer SSBD to guests by default.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
    master commit: cd53023df952cf0084be9ee3d15a90f8837049c2
    master date: 2018-05-21 14:20:06 +0100
---
 xen/arch/x86/domctl.c                       | 3 ++-
 xen/arch/x86/hvm/hvm.c                      | 3 ++-
 xen/arch/x86/traps.c                        | 3 ++-
 xen/include/public/arch-x86/cpufeatureset.h | 2 +-
 4 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 659dc9f4a2..ad5d20bc5a 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1389,7 +1389,8 @@ long arch_do_domctl(
                      * ignored) when STIBP isn't enumerated in hardware.
                      */
 
-                    if ( msr.value & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP) )
+                    if ( msr.value & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP |
+                                       (boot_cpu_has(X86_FEATURE_SSBD) ? 
SPEC_CTRL_SSBD : 0)) )
                         break;
                     v->arch.spec_ctrl = msr.value;
                     continue;
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index b989ac4990..3686faba74 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -4142,7 +4142,8 @@ int hvm_msr_write_intercept(unsigned int msr, uint64_t 
msr_content,
          * when STIBP isn't enumerated in hardware.
          */
 
-        if ( msr_content & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP) )
+        if ( msr_content & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP |
+                             (edx & cpufeat_mask(X86_FEATURE_SSBD) ? 
SPEC_CTRL_SSBD : 0)) )
             goto gp_fault; /* Rsvd bit set? */
 
         v->arch.spec_ctrl = msr_content;
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index f950e8d872..e7f197d336 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2747,7 +2747,8 @@ static int priv_op_write_msr(unsigned int reg, uint64_t 
val,
          * when STIBP isn't enumerated in hardware.
          */
 
-        if ( val & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP) )
+        if ( val & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP |
+                     (edx & cpufeat_mask(X86_FEATURE_SSBD) ? SPEC_CTRL_SSBD : 
0)) )
             break; /* Rsvd bit set? */
 
         curr->arch.spec_ctrl = val;
diff --git a/xen/include/public/arch-x86/cpufeatureset.h 
b/xen/include/public/arch-x86/cpufeatureset.h
index 93645bd8ae..70a17f73cd 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -239,7 +239,7 @@ XEN_CPUFEATURE(IBPB,          8*32+12) /*A  IBPB support 
only (no IBRS, used by
 XEN_CPUFEATURE(IBRSB,         9*32+26) /*A  IBRS and IBPB support (used by 
Intel) */
 XEN_CPUFEATURE(STIBP,         9*32+27) /*A! STIBP */
 XEN_CPUFEATURE(ARCH_CAPS,     9*32+29) /*   IA32_ARCH_CAPABILITIES MSR */
-XEN_CPUFEATURE(SSBD,          9*32+31) /*   MSR_SPEC_CTRL.SSBD available */
+XEN_CPUFEATURE(SSBD,          9*32+31) /*A  MSR_SPEC_CTRL.SSBD available */
 
 #endif /* XEN_CPUFEATURE */
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.8

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