[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen staging] x86/cpu: add support for zhaoxin x86 platform
commit 0de241637632a07a136b55b5363bfccf6fce40d5 Author: DavidWang <davidwang@xxxxxxxxxxx> AuthorDate: Thu Jul 5 15:13:28 2018 +0200 Commit: Jan Beulich <jbeulich@xxxxxxxx> CommitDate: Thu Jul 5 15:13:28 2018 +0200 x86/cpu: add support for zhaoxin x86 platform Zhaoxin is a x86 IC designer. Its SOC products support both CPU virtualization and I/O virtualization, which are compatible with Intel VMX and VT-d respectively. Zhaoxin has 'Shanghai' CPU vendor ID. Signed-off-by: DavidWang <davidwang@xxxxxxxxxxx> Acked-by: Jan Beulich <jbeulich@xxxxxxxx> --- xen/arch/x86/cpu/Makefile | 1 + xen/arch/x86/cpu/common.c | 1 + xen/arch/x86/cpu/cpu.h | 1 + xen/arch/x86/cpu/intel_cacheinfo.c | 4 +++- xen/arch/x86/cpu/shanghai.c | 28 ++++++++++++++++++++++++++++ xen/include/asm-x86/x86-vendors.h | 3 ++- 6 files changed, 36 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile index 74f23aee0f..34a01ca061 100644 --- a/xen/arch/x86/cpu/Makefile +++ b/xen/arch/x86/cpu/Makefile @@ -7,4 +7,5 @@ obj-y += common.o obj-y += intel.o obj-y += intel_cacheinfo.o obj-y += mwait-idle.o +obj-y += shanghai.o obj-y += vpmu.o vpmu_amd.o vpmu_intel.o diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index bdd45c30fb..e6a592256f 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -700,6 +700,7 @@ void __init early_cpu_init(void) intel_cpu_init(); amd_init_cpu(); centaur_init_cpu(); + shanghai_init_cpu(); early_cpu_detect(); } diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h index 4ac2034c69..2fcb931388 100644 --- a/xen/arch/x86/cpu/cpu.h +++ b/xen/arch/x86/cpu/cpu.h @@ -20,3 +20,4 @@ extern void display_cacheinfo(struct cpuinfo_x86 *c); int intel_cpu_init(void); int amd_init_cpu(void); int centaur_init_cpu(void); +int shanghai_init_cpu(void); diff --git a/xen/arch/x86/cpu/intel_cacheinfo.c b/xen/arch/x86/cpu/intel_cacheinfo.c index 4ffcf1b6a0..88b61fddfe 100644 --- a/xen/arch/x86/cpu/intel_cacheinfo.c +++ b/xen/arch/x86/cpu/intel_cacheinfo.c @@ -168,7 +168,9 @@ unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c) * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for * trace cache */ - if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) { + if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1 && + c->x86_vendor != X86_VENDOR_SHANGHAI) + { /* supports eax=2 call */ int i, j, n; int regs[4]; diff --git a/xen/arch/x86/cpu/shanghai.c b/xen/arch/x86/cpu/shanghai.c new file mode 100644 index 0000000000..9156c850fe --- /dev/null +++ b/xen/arch/x86/cpu/shanghai.c @@ -0,0 +1,28 @@ +#include <xen/bitops.h> +#include <xen/init.h> +#include <asm/processor.h> +#include "cpu.h" + +static void init_shanghai(struct cpuinfo_x86 *c) +{ + if ( cpu_has(c, X86_FEATURE_ITSC) ) + { + __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); + __set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability); + __set_bit(X86_FEATURE_TSC_RELIABLE, c->x86_capability); + } + + init_intel_cacheinfo(c); +} + +static const struct cpu_dev shanghai_cpu_dev = { + .c_vendor = " Shang", + .c_ident = {" Shanghai "}, + .c_init = init_shanghai, +}; + +int __init shanghai_init_cpu(void) +{ + cpu_devs[X86_VENDOR_SHANGHAI] = &shanghai_cpu_dev; + return 0; +} diff --git a/xen/include/asm-x86/x86-vendors.h b/xen/include/asm-x86/x86-vendors.h index cae5507bd0..c53d0b9baf 100644 --- a/xen/include/asm-x86/x86-vendors.h +++ b/xen/include/asm-x86/x86-vendors.h @@ -7,7 +7,8 @@ #define X86_VENDOR_INTEL 0 #define X86_VENDOR_AMD 1 #define X86_VENDOR_CENTAUR 2 -#define X86_VENDOR_NUM 3 +#define X86_VENDOR_SHANGHAI 3 +#define X86_VENDOR_NUM 4 #define X86_VENDOR_UNKNOWN 0xff #endif /* __XEN_X86_VENDORS_H__ */ -- generated by git-patchbot for /home/xen/git/xen.git#staging _______________________________________________ Xen-changelog mailing list Xen-changelog@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/xen-changelog
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