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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen staging] x86: Fix APIC MSR constant names
commit 689bc6244449fd988c32759201668738498ec261
Author: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Wed Mar 7 16:48:01 2018 +0000
Commit: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Wed Dec 5 21:01:23 2018 +0000
x86: Fix APIC MSR constant names
We currently have MSR_IA32_APICBASE and MSR_IA32_APICBASE_MSR which are
synonymous from a naming point of view, but refer to very different things.
Rename the x2APIC MSRs to MSR_X2APIC_*, which are shorter constants and
visually separate the register function from the generic APIC name. For the
case ranges, introduce MSR_X2APIC_LAST, rather than relying on the knowledge
that there are 0x3ff MSRs architecturally reserved for x2APIC functionality.
For functionality relating to the APIC_BASE MSR, use MSR_APIC_BASE for the
MSR
itself, but drop the MSR prefix from the other constants to shorten the
names.
In all cases, the fact that we are dealing with the APIC_BASE MSR is obvious
from the context.
No functional change (the combined binary is identical).
Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx>
Reviewed-by: Kevin Tian <kevin.tian@xxxxxxxxx>
Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
Reviewed-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
---
xen/arch/x86/apic.c | 66 ++++++++++++++++++++--------------------
xen/arch/x86/genapic/x2apic.c | 4 +--
xen/arch/x86/hvm/hvm.c | 8 ++---
xen/arch/x86/hvm/vlapic.c | 19 ++++++------
xen/arch/x86/hvm/vmx/vmx.c | 20 ++++++------
xen/include/asm-x86/hvm/vlapic.h | 6 ++--
xen/include/asm-x86/msr-index.h | 27 ++++++++--------
7 files changed, 76 insertions(+), 74 deletions(-)
diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index 7120107b0c..9db87f4f0e 100644
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -303,31 +303,31 @@ void disable_local_APIC(void)
if (enabled_via_apicbase) {
uint64_t msr_content;
- rdmsrl(MSR_IA32_APICBASE, msr_content);
- wrmsrl(MSR_IA32_APICBASE, msr_content &
- ~(MSR_IA32_APICBASE_ENABLE|MSR_IA32_APICBASE_EXTD));
+ rdmsrl(MSR_APIC_BASE, msr_content);
+ wrmsrl(MSR_APIC_BASE, msr_content &
+ ~(APIC_BASE_ENABLE | APIC_BASE_EXTD));
}
if ( kexecing && (current_local_apic_mode() != apic_boot_mode) )
{
uint64_t msr_content;
- rdmsrl(MSR_IA32_APICBASE, msr_content);
- msr_content &= ~(MSR_IA32_APICBASE_ENABLE|MSR_IA32_APICBASE_EXTD);
- wrmsrl(MSR_IA32_APICBASE, msr_content);
+ rdmsrl(MSR_APIC_BASE, msr_content);
+ msr_content &= ~(APIC_BASE_ENABLE | APIC_BASE_EXTD);
+ wrmsrl(MSR_APIC_BASE, msr_content);
switch ( apic_boot_mode )
{
case APIC_MODE_DISABLED:
break; /* Nothing to do - we did this above */
case APIC_MODE_XAPIC:
- msr_content |= MSR_IA32_APICBASE_ENABLE;
- wrmsrl(MSR_IA32_APICBASE, msr_content);
+ msr_content |= APIC_BASE_ENABLE;
+ wrmsrl(MSR_APIC_BASE, msr_content);
break;
case APIC_MODE_X2APIC:
- msr_content |= MSR_IA32_APICBASE_ENABLE;
- wrmsrl(MSR_IA32_APICBASE, msr_content);
- msr_content |= MSR_IA32_APICBASE_EXTD;
- wrmsrl(MSR_IA32_APICBASE, msr_content);
+ msr_content |= APIC_BASE_ENABLE;
+ wrmsrl(MSR_APIC_BASE, msr_content);
+ msr_content |= APIC_BASE_EXTD;
+ wrmsrl(MSR_APIC_BASE, msr_content);
break;
default:
printk("Default case when reverting #%d lapic to boot state\n",
@@ -479,12 +479,12 @@ static void __enable_x2apic(void)
{
uint64_t msr_content;
- rdmsrl(MSR_IA32_APICBASE, msr_content);
- if ( !(msr_content & MSR_IA32_APICBASE_EXTD) )
+ rdmsrl(MSR_APIC_BASE, msr_content);
+ if ( !(msr_content & APIC_BASE_EXTD) )
{
- msr_content |= MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_EXTD;
+ msr_content |= APIC_BASE_ENABLE | APIC_BASE_EXTD;
msr_content = (uint32_t)msr_content;
- wrmsrl(MSR_IA32_APICBASE, msr_content);
+ wrmsrl(MSR_APIC_BASE, msr_content);
}
}
@@ -744,10 +744,10 @@ int lapic_resume(void)
*/
if ( !x2apic_enabled )
{
- rdmsrl(MSR_IA32_APICBASE, msr_content);
- msr_content &= ~MSR_IA32_APICBASE_BASE;
- wrmsrl(MSR_IA32_APICBASE,
- msr_content | MSR_IA32_APICBASE_ENABLE | mp_lapic_addr);
+ rdmsrl(MSR_APIC_BASE, msr_content);
+ msr_content &= ~APIC_BASE_ADDR_MASK;
+ wrmsrl(MSR_APIC_BASE,
+ msr_content | APIC_BASE_ENABLE | mp_lapic_addr);
}
else
resume_x2apic();
@@ -818,7 +818,8 @@ static int __init detect_init_APIC (void)
if (enable_local_apic < 0)
return -1;
- if (rdmsr_safe(MSR_IA32_APICBASE, msr_content)) {
+ if ( rdmsr_safe(MSR_APIC_BASE, msr_content) )
+ {
printk("No local APIC present\n");
return -1;
}
@@ -839,11 +840,12 @@ static int __init detect_init_APIC (void)
* software for Intel P6 or later and AMD K7
* (Model > 1) or later.
*/
- if (!(msr_content & MSR_IA32_APICBASE_ENABLE)) {
+ if ( !(msr_content & APIC_BASE_ENABLE) )
+ {
printk("Local APIC disabled by BIOS -- reenabling.\n");
- msr_content &= ~MSR_IA32_APICBASE_BASE;
- msr_content |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
- wrmsrl(MSR_IA32_APICBASE, msr_content);
+ msr_content &= ~APIC_BASE_ADDR_MASK;
+ msr_content |= APIC_BASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
+ wrmsrl(MSR_APIC_BASE, msr_content);
enabled_via_apicbase = true;
}
}
@@ -860,8 +862,8 @@ static int __init detect_init_APIC (void)
mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
/* The BIOS may have set up the APIC at some other address */
- if (msr_content & MSR_IA32_APICBASE_ENABLE)
- mp_lapic_addr = msr_content & MSR_IA32_APICBASE_BASE;
+ if ( msr_content & APIC_BASE_ENABLE )
+ mp_lapic_addr = msr_content & APIC_BASE_ADDR_MASK;
if (nmi_watchdog != NMI_NONE)
nmi_watchdog = NMI_LOCAL_APIC;
@@ -1546,23 +1548,21 @@ void __init record_boot_APIC_mode(void)
apic_mode_to_str(apic_boot_mode));
}
-/* Look at the bits in MSR_IA32_APICBASE and work out which
- * APIC mode we are in */
+/* Look at the bits in MSR_APIC_BASE and work out which APIC mode we are in */
enum apic_mode current_local_apic_mode(void)
{
u64 msr_contents;
- rdmsrl(MSR_IA32_APICBASE, msr_contents);
+ rdmsrl(MSR_APIC_BASE, msr_contents);
/* Reading EXTD bit from the MSR is only valid if CPUID
* says so, else reserved */
- if ( boot_cpu_has(X86_FEATURE_X2APIC)
- && (msr_contents & MSR_IA32_APICBASE_EXTD) )
+ if ( boot_cpu_has(X86_FEATURE_X2APIC) && (msr_contents & APIC_BASE_EXTD) )
return APIC_MODE_X2APIC;
/* EN bit should always be valid as long as we can read the MSR
*/
- if ( msr_contents & MSR_IA32_APICBASE_ENABLE )
+ if ( msr_contents & APIC_BASE_ENABLE )
return APIC_MODE_XAPIC;
return APIC_MODE_DISABLED;
diff --git a/xen/arch/x86/genapic/x2apic.c b/xen/arch/x86/genapic/x2apic.c
index 7e2e89d881..334dae527e 100644
--- a/xen/arch/x86/genapic/x2apic.c
+++ b/xen/arch/x86/genapic/x2apic.c
@@ -254,8 +254,8 @@ void __init check_x2apic_preenabled(void)
return;
/* Check whether x2apic mode was already enabled by the BIOS. */
- rdmsr(MSR_IA32_APICBASE, lo, hi);
- if ( lo & MSR_IA32_APICBASE_EXTD )
+ rdmsr(MSR_APIC_BASE, lo, hi);
+ if ( lo & APIC_BASE_EXTD )
{
printk("x2APIC mode is already enabled by BIOS.\n");
x2apic_enabled = 1;
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index e2e420444f..46cb92e9bc 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -3410,11 +3410,11 @@ int hvm_msr_read_intercept(unsigned int msr, uint64_t
*msr_content)
*msr_content = hvm_msr_tsc_aux(v);
break;
- case MSR_IA32_APICBASE:
+ case MSR_APIC_BASE:
*msr_content = vcpu_vlapic(v)->hw.apic_base_msr;
break;
- case MSR_IA32_APICBASE_MSR ... MSR_IA32_APICBASE_MSR + 0x3ff:
+ case MSR_X2APIC_FIRST ... MSR_X2APIC_LAST:
if ( hvm_x2apic_msr_read(v, msr, msr_content) )
goto gp_fault;
break;
@@ -3569,7 +3569,7 @@ int hvm_msr_write_intercept(unsigned int msr, uint64_t
msr_content,
wrmsr_tsc_aux(msr_content);
break;
- case MSR_IA32_APICBASE:
+ case MSR_APIC_BASE:
if ( !vlapic_msr_set(vcpu_vlapic(v), msr_content) )
goto gp_fault;
break;
@@ -3578,7 +3578,7 @@ int hvm_msr_write_intercept(unsigned int msr, uint64_t
msr_content,
vlapic_tdt_msr_set(vcpu_vlapic(v), msr_content);
break;
- case MSR_IA32_APICBASE_MSR ... MSR_IA32_APICBASE_MSR + 0x3ff:
+ case MSR_X2APIC_FIRST ... MSR_X2APIC_LAST:
if ( hvm_x2apic_msr_write(v, msr, msr_content) )
goto gp_fault;
break;
diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c
index bdf946b25a..05afb7aed6 100644
--- a/xen/arch/x86/hvm/vlapic.c
+++ b/xen/arch/x86/hvm/vlapic.c
@@ -665,7 +665,7 @@ int hvm_x2apic_msr_read(struct vcpu *v, unsigned int msr,
uint64_t *msr_content)
#undef REGBLOCK
};
const struct vlapic *vlapic = vcpu_vlapic(v);
- uint32_t high = 0, reg = msr - MSR_IA32_APICBASE_MSR, offset = reg << 4;
+ uint32_t high = 0, reg = msr - MSR_X2APIC_FIRST, offset = reg << 4;
if ( !vlapic_x2apic_mode(vlapic) ||
(reg >= sizeof(readable) * 8) || !test_bit(reg, readable) )
@@ -960,7 +960,7 @@ int vlapic_apicv_write(struct vcpu *v, unsigned int offset)
int hvm_x2apic_msr_write(struct vcpu *v, unsigned int msr, uint64_t
msr_content)
{
struct vlapic *vlapic = vcpu_vlapic(v);
- uint32_t offset = (msr - MSR_IA32_APICBASE_MSR) << 4;
+ uint32_t offset = (msr - MSR_X2APIC_FIRST) << 4;
if ( !vlapic_x2apic_mode(vlapic) )
return X86EMUL_UNHANDLEABLE;
@@ -1067,11 +1067,11 @@ bool_t vlapic_msr_set(struct vlapic *vlapic, uint64_t
value)
if ( !has_vlapic(vlapic_domain(vlapic)) )
return 0;
- if ( (vlapic->hw.apic_base_msr ^ value) & MSR_IA32_APICBASE_ENABLE )
+ if ( (vlapic->hw.apic_base_msr ^ value) & APIC_BASE_ENABLE )
{
- if ( unlikely(value & MSR_IA32_APICBASE_EXTD) )
+ if ( unlikely(value & APIC_BASE_EXTD) )
return 0;
- if ( value & MSR_IA32_APICBASE_ENABLE )
+ if ( value & APIC_BASE_ENABLE )
{
vlapic_reset(vlapic);
vlapic->hw.disabled &= ~VLAPIC_HW_DISABLED;
@@ -1083,7 +1083,7 @@ bool_t vlapic_msr_set(struct vlapic *vlapic, uint64_t
value)
pt_may_unmask_irq(vlapic_domain(vlapic), NULL);
}
}
- else if ( ((vlapic->hw.apic_base_msr ^ value) & MSR_IA32_APICBASE_EXTD) &&
+ else if ( ((vlapic->hw.apic_base_msr ^ value) & APIC_BASE_EXTD) &&
unlikely(!vlapic_xapic_mode(vlapic)) )
return 0;
@@ -1360,10 +1360,9 @@ void vlapic_reset(struct vlapic *vlapic)
if ( !has_vlapic(v->domain) )
return;
- vlapic->hw.apic_base_msr = (MSR_IA32_APICBASE_ENABLE |
- APIC_DEFAULT_PHYS_BASE);
+ vlapic->hw.apic_base_msr = APIC_BASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
if ( v->vcpu_id == 0 )
- vlapic->hw.apic_base_msr |= MSR_IA32_APICBASE_BSP;
+ vlapic->hw.apic_base_msr |= APIC_BASE_BSP;
vlapic_set_reg(vlapic, APIC_ID, (v->vcpu_id * 2) << 24);
vlapic_do_init(vlapic);
@@ -1472,7 +1471,7 @@ static int lapic_load_hidden(struct domain *d,
hvm_domain_context_t *h)
if ( s->loaded.regs )
lapic_load_fixup(s);
- if ( !(s->hw.apic_base_msr & MSR_IA32_APICBASE_ENABLE) &&
+ if ( !(s->hw.apic_base_msr & APIC_BASE_ENABLE) &&
unlikely(vlapic_x2apic_mode(s)) )
return -EINVAL;
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 365eeb2886..7f77d1fd28 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -3059,19 +3059,19 @@ void vmx_vlapic_msr_changed(struct vcpu *v)
SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
if ( cpu_has_vmx_apic_reg_virt )
{
- for ( msr = MSR_IA32_APICBASE_MSR;
- msr <= MSR_IA32_APICBASE_MSR + 0xff; msr++ )
+ for ( msr = MSR_X2APIC_FIRST;
+ msr <= MSR_X2APIC_FIRST + 0xff; msr++ )
vmx_clear_msr_intercept(v, msr, VMX_MSR_R);
- vmx_set_msr_intercept(v, MSR_IA32_APICPPR_MSR, VMX_MSR_R);
- vmx_set_msr_intercept(v, MSR_IA32_APICTMICT_MSR, VMX_MSR_R);
- vmx_set_msr_intercept(v, MSR_IA32_APICTMCCT_MSR, VMX_MSR_R);
+ vmx_set_msr_intercept(v, MSR_X2APIC_PPR, VMX_MSR_R);
+ vmx_set_msr_intercept(v, MSR_X2APIC_TMICT, VMX_MSR_R);
+ vmx_set_msr_intercept(v, MSR_X2APIC_TMCCT, VMX_MSR_R);
}
if ( cpu_has_vmx_virtual_intr_delivery )
{
- vmx_clear_msr_intercept(v, MSR_IA32_APICTPR_MSR, VMX_MSR_W);
- vmx_clear_msr_intercept(v, MSR_IA32_APICEOI_MSR, VMX_MSR_W);
- vmx_clear_msr_intercept(v, MSR_IA32_APICSELF_MSR, VMX_MSR_W);
+ vmx_clear_msr_intercept(v, MSR_X2APIC_TPR, VMX_MSR_W);
+ vmx_clear_msr_intercept(v, MSR_X2APIC_EOI, VMX_MSR_W);
+ vmx_clear_msr_intercept(v, MSR_X2APIC_SELF, VMX_MSR_W);
}
}
else
@@ -3080,8 +3080,8 @@ void vmx_vlapic_msr_changed(struct vcpu *v)
}
if ( !(v->arch.hvm.vmx.secondary_exec_control &
SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE) )
- for ( msr = MSR_IA32_APICBASE_MSR;
- msr <= MSR_IA32_APICBASE_MSR + 0xff; msr++ )
+ for ( msr = MSR_X2APIC_FIRST;
+ msr <= MSR_X2APIC_FIRST + 0xff; msr++ )
vmx_set_msr_intercept(v, msr, VMX_MSR_RW);
vmx_update_secondary_exec_control(v);
diff --git a/xen/include/asm-x86/hvm/vlapic.h b/xen/include/asm-x86/hvm/vlapic.h
index 8dbec90ab0..4eb40750bc 100644
--- a/xen/include/asm-x86/hvm/vlapic.h
+++ b/xen/include/asm-x86/hvm/vlapic.h
@@ -50,13 +50,13 @@
#define vlapic_enabled(vlapic) (!vlapic_disabled(vlapic))
#define vlapic_base_address(vlapic) \
- ((vlapic)->hw.apic_base_msr & MSR_IA32_APICBASE_BASE)
+ ((vlapic)->hw.apic_base_msr & APIC_BASE_ADDR_MASK)
/* Only check EXTD bit as EXTD can't be set if it is disabled by hardware */
#define vlapic_x2apic_mode(vlapic) \
- ((vlapic)->hw.apic_base_msr & MSR_IA32_APICBASE_EXTD)
+ ((vlapic)->hw.apic_base_msr & APIC_BASE_EXTD)
#define vlapic_xapic_mode(vlapic) \
(!vlapic_hw_disabled(vlapic) && \
- !((vlapic)->hw.apic_base_msr & MSR_IA32_APICBASE_EXTD))
+ !((vlapic)->hw.apic_base_msr & APIC_BASE_EXTD))
/*
* Generic APIC bitmap vector update & search routines.
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 3faed27153..24d783a72d 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -326,18 +326,21 @@
#define MSR_IA32_TSC_ADJUST 0x0000003b
-#define MSR_IA32_APICBASE 0x0000001b
-#define MSR_IA32_APICBASE_BSP (1<<8)
-#define MSR_IA32_APICBASE_EXTD (1<<10)
-#define MSR_IA32_APICBASE_ENABLE (1<<11)
-#define MSR_IA32_APICBASE_BASE 0x000ffffffffff000ul
-#define MSR_IA32_APICBASE_MSR 0x800
-#define MSR_IA32_APICTPR_MSR 0x808
-#define MSR_IA32_APICPPR_MSR 0x80a
-#define MSR_IA32_APICEOI_MSR 0x80b
-#define MSR_IA32_APICTMICT_MSR 0x838
-#define MSR_IA32_APICTMCCT_MSR 0x839
-#define MSR_IA32_APICSELF_MSR 0x83f
+#define MSR_APIC_BASE 0x0000001b
+#define APIC_BASE_BSP (1<<8)
+#define APIC_BASE_EXTD (1<<10)
+#define APIC_BASE_ENABLE (1<<11)
+#define APIC_BASE_ADDR_MASK 0x000ffffffffff000ul
+
+#define MSR_X2APIC_FIRST 0x00000800
+#define MSR_X2APIC_LAST 0x00000bff
+
+#define MSR_X2APIC_TPR 0x00000808
+#define MSR_X2APIC_PPR 0x0000080a
+#define MSR_X2APIC_EOI 0x0000080b
+#define MSR_X2APIC_TMICT 0x00000838
+#define MSR_X2APIC_TMCCT 0x00000839
+#define MSR_X2APIC_SELF 0x0000083f
#define MSR_IA32_UCODE_WRITE 0x00000079
#define MSR_IA32_UCODE_REV 0x0000008b
--
generated by git-patchbot for /home/xen/git/xen.git#staging
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