[Xen-changelog] [xen staging] x86/msr: Definitions for MSR_INTEL_CORE_THREAD_COUNT

[patchbot@xxxxxxx]

commit d4120936bcd1695faf5b575f1259c58e31d2b18b
Author:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Fri Apr 5 12:26:30 2019 +0000
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Mon May 13 10:35:37 2019 +0100

    x86/msr: Definitions for MSR_INTEL_CORE_THREAD_COUNT
    
    This is a model specific register which details the current configuration
    cores and threads in the package.  Because of how Hyperthread and Core
    configuration works works in firmware, the MSR it is de-facto constant and
    will remain unchanged until the next system reset.
    
    It is a read only MSR (so unilaterally reject writes), but for now retain 
its
    leaky-on-read properties.  Further CPUID/MSR work is required before we can
    start virtualising a consistent topology to the guest, and retaining the old
    behaviour is the safest course of action.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/msr.c              | 5 +++++
 xen/include/asm-x86/msr-index.h | 4 ++++
 2 files changed, 9 insertions(+)

diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index 0049a73bc7..883b57b2d5 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -234,6 +234,10 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t 
*val)
                                    ARRAY_SIZE(msrs->dr_mask))];
         break;
 
+        /*
+         * TODO: Implement when we have better topology representation.
+    case MSR_INTEL_CORE_THREAD_COUNT:
+         */
     default:
         return X86EMUL_UNHANDLEABLE;
     }
@@ -263,6 +267,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
     {
         uint64_t rsvd;
 
+    case MSR_INTEL_CORE_THREAD_COUNT:
     case MSR_INTEL_PLATFORM_INFO:
     case MSR_ARCH_CAPABILITIES:
         /* Read-only */
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 11512d4250..389f95f890 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -32,6 +32,10 @@
 #define EFER_KNOWN_MASK                (EFER_SCE | EFER_LME | EFER_LMA | 
EFER_NX | \
                                 EFER_SVME | EFER_FFXSE)
 
+#define MSR_INTEL_CORE_THREAD_COUNT     0x00000035
+#define MSR_CTC_THREAD_MASK             0x0000ffff
+#define MSR_CTC_CORE_MASK               0xffff0000
+
 /* Speculation Controls. */
 #define MSR_SPEC_CTRL                  0x00000048
 #define SPEC_CTRL_IBRS                 (_AC(1, ULL) << 0)
--
generated by git-patchbot for /home/xen/git/xen.git#staging

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