[Xen-changelog] [xen staging-4.9] x86/spec-ctrl: Misc non-functional cleanup

[patchbot@xxxxxxx]

commit 3384ea4ab0accacd553ae595f970a15ecebd776d
Author:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Wed Sep 12 14:36:00 2018 +0100
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Tue May 14 15:43:28 2019 +0100

    x86/spec-ctrl: Misc non-functional cleanup
    
     * Identify BTI in the spec_ctrl_{enter,exit}_idle() comments, as other
       mitigations will shortly appear.
     * Use alternative_input() and cover the lack of memory cobber with a 
further
       barrier.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
    (cherry picked from commit 9b62eba6c429c327e1507816bef403ccc87357ae)
---
 xen/include/asm-x86/spec_ctrl.h | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/xen/include/asm-x86/spec_ctrl.h b/xen/include/asm-x86/spec_ctrl.h
index c8463544ae..4983071901 100644
--- a/xen/include/asm-x86/spec_ctrl.h
+++ b/xen/include/asm-x86/spec_ctrl.h
@@ -61,6 +61,8 @@ static always_inline void spec_ctrl_enter_idle(struct 
cpu_info *info)
     uint32_t val = 0;
 
     /*
+     * Branch Target Injection:
+     *
      * Latch the new shadow value, then enable shadowing, then update the MSR.
      * There are no SMP issues here; only local processor ordering concerns.
      */
@@ -68,8 +70,9 @@ static always_inline void spec_ctrl_enter_idle(struct 
cpu_info *info)
     barrier();
     info->spec_ctrl_flags |= SCF_use_shadow;
     barrier();
-    asm volatile ( ALTERNATIVE(ASM_NOP3, "wrmsr", X86_FEATURE_SC_MSR_IDLE)
-                   :: "a" (val), "c" (MSR_SPEC_CTRL), "d" (0) : "memory" );
+    alternative_input(ASM_NOP3, "wrmsr", X86_FEATURE_SC_MSR_IDLE,
+                      "a" (val), "c" (MSR_SPEC_CTRL), "d" (0));
+    barrier();
 }
 
 /* WARNING! `ret`, `call *`, `jmp *` not safe before this call. */
@@ -78,13 +81,16 @@ static always_inline void spec_ctrl_exit_idle(struct 
cpu_info *info)
     uint32_t val = info->xen_spec_ctrl;
 
     /*
+     * Branch Target Injection:
+     *
      * Disable shadowing before updating the MSR.  There are no SMP issues
      * here; only local processor ordering concerns.
      */
     info->spec_ctrl_flags &= ~SCF_use_shadow;
     barrier();
-    asm volatile ( ALTERNATIVE(ASM_NOP3, "wrmsr", X86_FEATURE_SC_MSR_IDLE)
-                   :: "a" (val), "c" (MSR_SPEC_CTRL), "d" (0) : "memory" );
+    alternative_input(ASM_NOP3, "wrmsr", X86_FEATURE_SC_MSR_IDLE,
+                      "a" (val), "c" (MSR_SPEC_CTRL), "d" (0));
+    barrier();
 }
 
 #endif /* !__X86_SPEC_CTRL_H__ */
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.9

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