[Xen-changelog] [xen staging] x86emul: support AVX512{F, DQ} uint-to-FP conversion insns

[patchbot@xxxxxxx]

commit 24ed2c86bd4fac551693f03d2a6f90e48761c597
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Fri May 24 10:24:11 2019 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Fri May 24 10:24:11 2019 +0200

    x86emul: support AVX512{F,DQ} uint-to-FP conversion insns
    
    Some "manual" overrides of disp8scale are needed here again. In
    particular code ends up simpler when using d8s_dq64 in the
    twobyte_table[] entry.
    
    Test harness additions will be done once the reverse conversions are
    also available.
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
 tools/tests/x86_emulator/evex-disp8.c  |  6 ++++++
 xen/arch/x86/x86_emulate/x86_emulate.c | 17 +++++++++++++----
 2 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/tools/tests/x86_emulator/evex-disp8.c 
b/tools/tests/x86_emulator/evex-disp8.c
index 0c9989ebfa..50a328125d 100644
--- a/tools/tests/x86_emulator/evex-disp8.c
+++ b/tools/tests/x86_emulator/evex-disp8.c
@@ -127,6 +127,10 @@ static const struct test avx512f_all[] = {
     INSN(cvttps2dq,    f3,   0f, 5b,    vl,      d, vl),
     INSN(cvttsd2si,    f2,   0f, 2c,    el,      q, el),
     INSN(cvttss2si,    f3,   0f, 2c,    el,      d, el),
+    INSN(cvtudq2pd,    f3,   0f, 7a,    vl_2,    d, vl),
+    INSN(cvtudq2ps,    f2,   0f, 7a,    vl,      d, vl),
+    INSN(cvtusi2sd,    f2,   0f, 7b,    el,   dq64, el),
+    INSN(cvtusi2ss,    f3,   0f, 7b,    el,   dq64, el),
     INSN_FP(div,             0f, 5e),
     INSN(fmadd132,     66, 0f38, 98,    vl,     sd, vl),
     INSN(fmadd132,     66, 0f38, 99,    el,     sd, el),
@@ -416,6 +420,8 @@ static const struct test avx512dq_all[] = {
     INSN(cvtqq2ps,         ,   0f, 5b,   vl,  q, vl),
     INSN(cvttpd2qq,      66,   0f, 7a,   vl,  q, vl),
     INSN(cvttps2qq,      66,   0f, 7a, vl_2,  d, vl),
+    INSN(cvtuqq2pd,      f3,   0f, 7a,   vl,  q, vl),
+    INSN(cvtuqq2ps,      f2,   0f, 7a,   vl,  q, vl),
     INSN_PFP(or,               0f, 56),
 //       pmovd2m,        f3, 0f38, 39,        d
 //       pmovm2,         f3, 0f38, 38,       dq
diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c 
b/xen/arch/x86/x86_emulate/x86_emulate.c
index a48ab2411e..cc127a066a 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -326,7 +326,7 @@ static const struct twobyte_table {
     [0x78] = { ImplicitOps|ModRM },
     [0x79] = { DstReg|SrcMem|ModRM, simd_packed_int },
     [0x7a] = { DstImplicit|SrcMem|ModRM|Mov, simd_packed_fp, d8s_vl },
-    [0x7b] = { DstImplicit|SrcMem|ModRM|Mov, simd_other, d8s_vl },
+    [0x7b] = { DstImplicit|SrcMem|ModRM|Mov, simd_other, d8s_dq64 },
     [0x7c ... 0x7d] = { DstImplicit|SrcMem|ModRM, simd_other },
     [0x7e] = { DstMem|SrcImplicit|ModRM|Mov, simd_none, d8s_dq64 },
     [0x7f] = { DstMem|SrcImplicit|ModRM|Mov, simd_packed_int, d8s_vl },
@@ -3053,12 +3053,16 @@ x86_decode(
                     --disp8scale;
                 break;
 
-            case 0x7a: /* vcvttps2qq needs special casing */
-            case 0x7b: /* vcvtps2qq needs special casing */
-                if ( disp8scale && evex.pfx == vex_66 && !evex.w && !evex.brs )
+            case 0x7a: /* vcvttps2qq and vcvtudq2pd need special casing */
+                if ( disp8scale && evex.pfx != vex_f2 && !evex.w && !evex.brs )
                     --disp8scale;
                 break;
 
+            case 0x7b: /* vcvtp{s,d}2qq need special casing */
+                if ( disp8scale && evex.pfx == vex_66 )
+                    disp8scale = (evex.brs ? 2 : 3 + evex.lr) + evex.w;
+                break;
+
             case 0x7e: /* vmovq xmm/m64,xmm needs special casing */
                 if ( disp8scale == 2 && evex.pfx == vex_f3 )
                     disp8scale = 3;
@@ -6188,6 +6192,7 @@ x86_emulate(
         goto simd_0f_rm;
 
     CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x2a): /* vcvtsi2s{s,d} r/m,xmm,xmm */
+    CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x7b): /* vcvtusi2s{s,d} r/m,xmm,xmm */
         generate_exception_if(evex.opmsk || (ea.type != OP_REG && evex.brs),
                               EXC_UD);
         host_and_vcpu_must_have(avx512f);
@@ -6654,6 +6659,8 @@ x86_emulate(
         /* fall through */
     case X86EMUL_OPC_EVEX(0x0f, 0x5b):    /* vcvtdq2ps [xyz]mm/mem,[xyz]mm{k} 
*/
                                           /* vcvtqq2ps [xyz]mm/mem,{x,y}mm{k} 
*/
+    case X86EMUL_OPC_EVEX_F2(0x0f, 0x7a): /* vcvtudq2ps [xyz]mm/mem,[xyz]mm{k} 
*/
+                                          /* vcvtuqq2ps [xyz]mm/mem,{x,y}mm{k} 
*/
         if ( evex.w )
             host_and_vcpu_must_have(avx512dq);
         else
@@ -7334,6 +7341,8 @@ x86_emulate(
     case X86EMUL_OPC_EVEX_F2(0x0f, 0xe6):   /* vcvtpd2dq 
[xyz]mm/mem,{x,y}mm{k} */
         generate_exception_if(!evex.w, EXC_UD);
         /* fall through */
+    case X86EMUL_OPC_EVEX_F3(0x0f, 0x7a):   /* vcvtudq2pd 
{x,y}mm/mem,[xyz]mm{k} */
+                                            /* vcvtuqq2pd 
[xyz]mm/mem,[xyz]mm{k} */
     case X86EMUL_OPC_EVEX_F3(0x0f, 0xe6):   /* vcvtdq2pd 
{x,y}mm/mem,[xyz]mm{k} */
                                             /* vcvtqq2pd 
[xyz]mm/mem,[xyz]mm{k} */
         if ( evex.pfx != vex_f3 )
--
generated by git-patchbot for /home/xen/git/xen.git#staging

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