[Xen-changelog] [xen staging] x86/cpu/mtrr: Add Hygon Dhyana support to get TOP_MEM2

[patchbot@xxxxxxx]

commit 1c07b0135a715021142c549eae6ad5c52acd9eb6
Author:     Pu Wen <puwen@xxxxxxxx>
AuthorDate: Thu Apr 4 21:45:56 2019 +0800
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Thu Jun 6 15:28:20 2019 +0100

    x86/cpu/mtrr: Add Hygon Dhyana support to get TOP_MEM2
    
    The Hygon Dhyana CPU supports the MSR way to get TOP_MEM2. So add Hygon
    Dhyana support to print the value of TOP_MEM2.
    
    Signed-off-by: Pu Wen <puwen@xxxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/cpu/mtrr/generic.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/cpu/mtrr/generic.c b/xen/arch/x86/cpu/mtrr/generic.c
index 8f9cf1b1d7..94ee7d61ad 100644
--- a/xen/arch/x86/cpu/mtrr/generic.c
+++ b/xen/arch/x86/cpu/mtrr/generic.c
@@ -217,8 +217,9 @@ static void __init print_mtrr_state(const char *level)
                        printk("%s  %u disabled\n", level, i);
        }
 
-       if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD
-           && boot_cpu_data.x86 >= 0xf) {
+       if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
+            boot_cpu_data.x86 >= 0xf) ||
+            boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
                uint64_t syscfg, tom2;
 
                rdmsrl(MSR_K8_SYSCFG, syscfg);
--
generated by git-patchbot for /home/xen/git/xen.git#staging

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