[Xen-changelog] [xen staging] x86/traps: Add Hygon Dhyana support

[patchbot@xxxxxxx]

commit c6d427a617b3c5fd7ad716dc24e1352f7ffe024e
Author:     Pu Wen <puwen@xxxxxxxx>
AuthorDate: Thu Apr 4 21:47:54 2019 +0800
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Thu Jun 6 15:28:21 2019 +0100

    x86/traps: Add Hygon Dhyana support
    
    The Hygon Dhyana processor has the methold to get the last exception
    source IP from MSR0000_01DD. So add support for it if the boot param
    ler is true.
    
    Signed-off-by: Pu Wen <puwen@xxxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/traps.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index ba1053fa68..8097ef3bf5 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -1973,6 +1973,9 @@ static unsigned int calc_ler_msr(void)
             return MSR_IA32_LASTINTFROMIP;
         }
         break;
+
+    case X86_VENDOR_HYGON:
+        return MSR_IA32_LASTINTFROMIP;
     }
 
     return 0;
--
generated by git-patchbot for /home/xen/git/xen.git#staging

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