[Xen-changelog] [xen staging] xen/arm: Don't boot Xen on platform using AIVIVT instruction caches

[patchbot@xxxxxxx]

commit 65948881d02fd593fa0fc07447919cf378d08390
Author:     Julien Grall <julien.grall@xxxxxxx>
AuthorDate: Mon May 13 16:02:18 2019 +0100
Commit:     Julien Grall <julien.grall@xxxxxxx>
CommitDate: Wed Jun 12 16:13:36 2019 +0100

    xen/arm: Don't boot Xen on platform using AIVIVT instruction caches
    
    The AIVIVT is a type of instruction cache available on Armv7. This is
    the only cache not implementing the IVIPT extension and therefore
    requiring specific care.
    
    To simplify maintenance requirements, Xen will not boot on platform
    using AIVIVT cache.
    
    This should not be an issue because Xen Arm32 can only boot on a small
    number of processors (see arch/arm/arm32/proc-v7.S). All of them are
    not using AIVIVT cache.
    
    Signed-off-by: Julien Grall <julien.grall@xxxxxxx>
    Acked-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>
---
 xen/arch/arm/setup.c            | 5 +++++
 xen/include/asm-arm/processor.h | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
index 5af49c7a08..9ff6f83981 100644
--- a/xen/arch/arm/setup.c
+++ b/xen/arch/arm/setup.c
@@ -526,10 +526,15 @@ static void __init setup_mm(unsigned long dtb_paddr, 
size_t dtb_size)
     unsigned long boot_mfn_start, boot_mfn_end;
     int i;
     void *fdt;
+    const uint32_t ctr = READ_CP32(CTR);
 
     if ( !bootinfo.mem.nr_banks )
         panic("No memory bank\n");
 
+    /* We only supports instruction caches implementing the IVIPT extension. */
+    if ( ((ctr >> CTR_L1Ip_SHIFT) & CTR_L1Ip_MASK) == CTR_L1Ip_AIVIVT )
+        panic("AIVIVT instruction cache not supported\n");
+
     init_pdx();
 
     ram_start = bootinfo.mem.bank[0].start;
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index a54583baeb..bbcba061ca 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -6,6 +6,11 @@
 #endif
 #include <public/arch-arm.h>
 
+/* CTR Cache Type Register */
+#define CTR_L1Ip_MASK       0x3
+#define CTR_L1Ip_SHIFT      14
+#define CTR_L1Ip_AIVIVT     0x1
+
 /* MIDR Main ID Register */
 #define MIDR_REVISION_MASK      0xf
 #define MIDR_RESIVION(midr)     ((midr) & MIDR_REVISION_MASK)
--
generated by git-patchbot for /home/xen/git/xen.git#staging

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