[Xen-changelog] [xen stable-4.8] x86/msr: Definitions for MSR_INTEL_CORE_THREAD_COUNT

[patchbot@xxxxxxx]

commit 194b7a250edae89018ee0b00ce313b389c3bf446
Author:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Fri Apr 5 12:26:30 2019 +0000
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Tue May 14 15:48:54 2019 +0100

    x86/msr: Definitions for MSR_INTEL_CORE_THREAD_COUNT
    
    This is a model specific register which details the current configuration
    cores and threads in the package.  Because of how Hyperthread and Core
    configuration works works in firmware, the MSR it is de-facto constant and
    will remain unchanged until the next system reset.
    
    It is a read only MSR (so unilaterally reject writes), but for now retain 
its
    leaky-on-read properties.  Further CPUID/MSR work is required before we can
    start virtualising a consistent topology to the guest, and retaining the old
    behaviour is the safest course of action.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
    (cherry picked from commit d4120936bcd1695faf5b575f1259c58e31d2b18b)
---
 xen/arch/x86/hvm/hvm.c          | 1 +
 xen/arch/x86/traps.c            | 1 +
 xen/include/asm-x86/msr-index.h | 4 ++++
 3 files changed, 6 insertions(+)

diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 9582950043..23d6f09d8a 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -4179,6 +4179,7 @@ int hvm_msr_write_intercept(unsigned int msr, uint64_t 
msr_content,
         wrmsrl(MSR_FLUSH_CMD, msr_content);
         break;
 
+    case MSR_INTEL_CORE_THREAD_COUNT:
     case MSR_ARCH_CAPABILITIES:
         /* Read-only */
     case MSR_TSX_FORCE_ABORT:
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 404bdce717..232d1b05d4 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2744,6 +2744,7 @@ static int priv_op_write_msr(unsigned int reg, uint64_t 
val,
             wrmsrl(reg, val);
         return X86EMUL_OKAY;
 
+    case MSR_INTEL_CORE_THREAD_COUNT:
     case MSR_INTEL_PLATFORM_INFO:
     case MSR_ARCH_CAPABILITIES:
         /* The MSR is read-only. */
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 29ece6a47e..54f3a66047 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -34,6 +34,10 @@
 #define EFER_KNOWN_MASK                (EFER_SCE | EFER_LME | EFER_LMA | 
EFER_NX | \
                                 EFER_SVME | EFER_LMSLE | EFER_FFXSE)
 
+#define MSR_INTEL_CORE_THREAD_COUNT     0x00000035
+#define MSR_CTC_THREAD_MASK             0x0000ffff
+#define MSR_CTC_CORE_MASK               0xffff0000
+
 /* Speculation Controls. */
 #define MSR_SPEC_CTRL                  0x00000048
 #define SPEC_CTRL_IBRS                 (_AC(1, ULL) << 0)
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.8

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