[Xen-changelog] [xen staging] x86/cpuid: Fix Lisbon/Magny-Cours Opterons WRT SSSE3/SSE4A

[patchbot@xxxxxxx]

commit a0bfdf64d9d124fcc1f7ff194e0a46a7e2a90f34
Author:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Tue Nov 19 16:40:26 2019 +0000
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Wed Nov 20 12:37:59 2019 +0000

    x86/cpuid: Fix Lisbon/Magny-Cours Opterons WRT SSSE3/SSE4A
    
    c/s ff66ccefe5 "x86/CPUID: adjust SSEn dependencies" made SSE4A depend on
    SSSE3, but these processors really do have have SSE4A without SSSE3.
    
    This manifests as an upgrade regression, as the SSE4A feature disappears 
from
    view.
    
    Adjust the SSE4A feature to depend on SSE3 rather than SSSE3.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
    Release-acked-by: Juergen Gross <jgross@xxxxxxxx>
---
 xen/tools/gen-cpuid.py | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
index 434a6ebf04..2e76f9abc0 100755
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -205,9 +205,10 @@ def crunch_numbers(state):
         # than to SSE.
         SSE2: [SSE3, LM, AESNI, PCLMULQDQ, SHA, GFNI],
 
-        # Other SSEn each depend on their predecessor versions.
-        SSE3: [SSSE3],
-        SSSE3: [SSE4_1, SSE4A],
+        # Other SSEn each depend on their predecessor versions.  AMD
+        # Lisbon/Magny-Cours processors implemented SSE4A without SSSE3.
+        SSE3: [SSSE3, SSE4A],
+        SSSE3: [SSE4_1],
         SSE4_1: [SSE4_2],
 
         # AMD specify no relationship between POPCNT and SSE4.2.  Intel
--
generated by git-patchbot for /home/xen/git/xen.git#staging

_______________________________________________
Xen-changelog mailing list
Xen-changelog@xxxxxxxxxxxxxxxxxxxx
https://lists.xenproject.org/xen-changelog