[Xen-changelog] [xen staging-4.11] x86: avoid HPET use on certain Intel platforms

[patchbot@xxxxxxx]

commit d35cbee6e105723e7e1f9ecbb4bb51cb94ec6b47
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Wed Dec 11 15:32:53 2019 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Wed Dec 11 15:32:53 2019 +0100

    x86: avoid HPET use on certain Intel platforms
    
    Linux commit fc5db58539b49351e76f19817ed1102bf7c712d0 says
    
    "Some Coffee Lake platforms have a skewed HPET timer once the SoCs entered
     PC10, which in consequence marks TSC as unstable because HPET is used as
     watchdog clocksource for TSC."
    
    Follow this for Xen as well. Looking at its patch context made me notice
    they have a pre-existing quirk for Bay Trail as well. The comment there,
    however, points at a Cherry Trail document. Looking at the datasheets of
    both, there appear to be similar issues, so go beyond Linux'es coverage
    and exclude both. Also key the disable on the PCI IDs of the actual
    affected devices, rather than those of 00:00.0.
    
    Apply the workarounds only when the use of HPET was not explicitly
    requested on the command line and when use of (deep) C-states was not
    disabled.
    
    Adjust a few types in touched or nearby code at the same time.
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    master commit: d5294a302c8441191d47888452958aea25243723
    master date: 2019-12-03 14:14:44 +0100
---
 xen/arch/x86/time.c | 38 ++++++++++++++++++++++++++++++++++----
 1 file changed, 34 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c
index c342d00732..430fba1e66 100644
--- a/xen/arch/x86/time.c
+++ b/xen/arch/x86/time.c
@@ -18,6 +18,7 @@
 #include <xen/timer.h>
 #include <xen/smp.h>
 #include <xen/irq.h>
+#include <xen/pci_ids.h>
 #include <xen/softirq.h>
 #include <xen/efi.h>
 #include <xen/cpuidle.h>
@@ -364,12 +365,41 @@ static u64 read_hpet_count(void)
     return hpet_read32(HPET_COUNTER);
 }
 
-static s64 __init init_hpet(struct platform_timesource *pts)
+static int64_t __init init_hpet(struct platform_timesource *pts)
 {
-    u64 hpet_rate = hpet_setup(), start;
-    u32 count, target;
+    uint64_t hpet_rate, start;
+    uint32_t count, target;
 
-    if ( hpet_rate == 0 )
+    if ( hpet_address && strcmp(opt_clocksource, pts->id) &&
+         cpuidle_using_deep_cstate() )
+    {
+        if ( pci_conf_read16(0, 0, 0x1f, 0,
+                             PCI_VENDOR_ID) == PCI_VENDOR_ID_INTEL )
+            switch ( pci_conf_read16(0, 0, 0x1f, 0, PCI_DEVICE_ID) )
+            {
+            /* HPET on Bay Trail platforms will halt in deep C states. */
+            case 0x0f1c:
+            /* HPET on Cherry Trail platforms will halt in deep C states. */
+            case 0x229c:
+                hpet_address = 0;
+                break;
+            }
+
+        /*
+         * Some Coffee Lake platforms have a skewed HPET timer once the SoCs
+         * entered PC10.
+         */
+        if ( pci_conf_read16(0, 0, 0, 0,
+                             PCI_VENDOR_ID) == PCI_VENDOR_ID_INTEL &&
+             pci_conf_read16(0, 0, 0, 0,
+                             PCI_DEVICE_ID) == 0x3ec4 )
+            hpet_address = 0;
+
+        if ( !hpet_address )
+            printk("Disabling HPET for being unreliable\n");
+    }
+
+    if ( (hpet_rate = hpet_setup()) == 0 )
         return 0;
 
     pts->frequency = hpet_rate;
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.11

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