[Xen-changelog] [xen staging] x86emul: correct LFS et al handling for 64-bit mode

[patchbot@xxxxxxx]

commit ffa21ea53034a3aebcf20c5cf737961f9209d34a
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Mon Dec 16 17:35:50 2019 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Mon Dec 16 17:35:50 2019 +0100

    x86emul: correct LFS et al handling for 64-bit mode
    
    AMD and friends explicitly specify that 64-bit operands aren't possible
    for these insns. Nevertheless REX.W isn't fully ignored: It still
    cancels a possible operand size override (0x66). Intel otoh explicitly
    provides for 64-bit operands on the respective insn page of the SDM.
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
 xen/arch/x86/x86_emulate/x86_emulate.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c 
b/xen/arch/x86/x86_emulate/x86_emulate.c
index d793bffa04..742280de23 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -2640,6 +2640,15 @@ x86_decode_twobyte(
         }
         break;
 
+    case 0xb2: /* lss */
+    case 0xb4: /* lfs */
+    case 0xb5: /* lgs */
+        /* REX.W ignored on a vendor-dependent basis. */
+        if ( op_bytes == 8 &&
+             (ctxt->cpuid->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) )
+            op_bytes = 4;
+        break;
+
     case 0xb8: /* jmpe / popcnt */
         if ( rep_prefix() )
             ctxt->opcode |= MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK);
--
generated by git-patchbot for /home/xen/git/xen.git#staging

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