[Xen-changelog] [xen staging] x86: explicitly disallow guest access to PPIN

[patchbot@xxxxxxx]

commit 619a7119da6a57ffe8bdd0f382e011eef05fbec2
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Fri Dec 20 16:30:13 2019 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Fri Dec 20 16:30:13 2019 +0100

    x86: explicitly disallow guest access to PPIN
    
    To fulfill the "protected" in its name, don't let the real hardware
    values leak. While we could report a control register value expressing
    this (which I would have preferred), unconditionally raise #GP for all
    accesses (in the interest of getting this done).
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
 xen/arch/x86/msr.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index da504ce7ae..785574de67 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -136,6 +136,10 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t 
*val)
     case MSR_TSX_CTRL:
     case MSR_AMD64_LWP_CFG:
     case MSR_AMD64_LWP_CBADDR:
+    case MSR_PPIN_CTL:
+    case MSR_PPIN:
+    case MSR_AMD_PPIN_CTL:
+    case MSR_AMD_PPIN:
         /* Not offered to guests. */
         goto gp_fault;
 
@@ -279,6 +283,10 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
     case MSR_TSX_CTRL:
     case MSR_AMD64_LWP_CFG:
     case MSR_AMD64_LWP_CBADDR:
+    case MSR_PPIN_CTL:
+    case MSR_PPIN:
+    case MSR_AMD_PPIN_CTL:
+    case MSR_AMD_PPIN:
         /* Not offered to guests. */
         goto gp_fault;
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging

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