[Xen-changelog] [xen staging] x86/msr: Virtualise MSR_PLATFORM_ID properly

[patchbot@xxxxxxx]

commit 691265f96097d4fe3e46ff4267451d49b30143e6
Author:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Tue Apr 30 12:07:04 2019 +0100
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Thu Feb 20 17:29:50 2020 +0000

    x86/msr: Virtualise MSR_PLATFORM_ID properly
    
    This is an Intel-only, read-only MSR related to microcode loading.  Expose 
it
    in similar circumstances as the PATCHLEVEL MSR.
    
    This should have been alongside c/s 013896cb8b2 "x86/msr: Fix handling of
    MSR_AMD_PATCHLEVEL/MSR_IA32_UCODE_REV"
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/msr.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index 785574de67..1cea777680 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -143,6 +143,13 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t 
*val)
         /* Not offered to guests. */
         goto gp_fault;
 
+    case MSR_IA32_PLATFORM_ID:
+        if ( !(cp->x86_vendor & X86_VENDOR_INTEL) ||
+             !(boot_cpu_data.x86_vendor & X86_VENDOR_INTEL) )
+            goto gp_fault;
+        rdmsrl(MSR_IA32_PLATFORM_ID, *val);
+        break;
+
     case MSR_AMD_PATCHLEVEL:
         BUILD_BUG_ON(MSR_IA32_UCODE_REV != MSR_AMD_PATCHLEVEL);
         /*
@@ -275,6 +282,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
     {
         uint64_t rsvd;
 
+    case MSR_IA32_PLATFORM_ID:
     case MSR_INTEL_CORE_THREAD_COUNT:
     case MSR_INTEL_PLATFORM_INFO:
     case MSR_ARCH_CAPABILITIES:
--
generated by git-patchbot for /home/xen/git/xen.git#staging

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