[Xen-changelog] [xen staging] x86/mce: add Xeon Icelake to list of CPUs that support PPIN

[patchbot@xxxxxxx]

commit cb4684e34602810c93c1e88adfd51d0e17177a99
Author:     Tony Luck <tony.luck@xxxxxxxxx>
AuthorDate: Mon Mar 2 15:40:09 2020 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Mon Mar 2 15:40:09 2020 +0100

    x86/mce: add Xeon Icelake to list of CPUs that support PPIN
    
    New CPU model, same MSRs to control and read the inventory number.
    
    Signed-off-by: Tony Luck <tony.luck@xxxxxxxxx>
    [Linux commit dc6b025de95bcd22ff37c4fabb022ec8a027abf1]
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
 xen/arch/x86/cpu/mcheck/mce_intel.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c 
b/xen/arch/x86/cpu/mcheck/mce_intel.c
index 6f23ea5329..29b9983172 100644
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -871,6 +871,7 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
     case 0x55: /* Skylake X */
     case 0x56: /* Broadwell Xeon D */
     case 0x57: /* Knights Landing */
+    case 0x6a: /* Icelake X */
     case 0x85: /* Knights Mill */
 
         if ( (c != &boot_cpu_data && !ppin_msr) ||
--
generated by git-patchbot for /home/xen/git/xen.git#staging

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