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[qemu-xen staging-4.13] s390x/tcg: Fix VERIM with 32/64 bit elements

commit 499a5d6bb47ec8be73fc47a37952c4d595957232
Author:     David Hildenbrand <david@xxxxxxxxxx>
AuthorDate: Wed Aug 14 17:12:42 2019 +0200
Commit:     Michael Roth <mdroth@xxxxxxxxxxxxxxxxxx>
CommitDate: Sun Oct 27 23:31:08 2019 -0500

    s390x/tcg: Fix VERIM with 32/64 bit elements
    Wrong order of operands. The constant always comes last. Makes QEMU crash
    reliably on specific git fetch invocations.
    Reported-by: Stefano Brivio <sbrivio@xxxxxxxxxx>
    Signed-off-by: David Hildenbrand <david@xxxxxxxxxx>
    Message-Id: <20190814151242.27199-1-david@xxxxxxxxxx>
    Reviewed-by: Cornelia Huck <cohuck@xxxxxxxxxx>
    Fixes: 5c4b0ab460ef ("s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT 
    Cc: qemu-stable@xxxxxxxxxx
    Signed-off-by: Cornelia Huck <cohuck@xxxxxxxxxx>
    (cherry picked from commit 25bcb45d1b81d22634daa2b1a2d8bee746ac129b)
    Signed-off-by: Michael Roth <mdroth@xxxxxxxxxxxxxxxxxx>
 target/s390x/translate_vx.inc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 41d5cf869f..0caddb3958 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -213,7 +213,7 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t 
reg, TCGv_i64 enr,
                        vec_full_reg_offset(v3), ptr, 16, 16, data, fn)
 #define gen_gvec_3i(v1, v2, v3, c, gen) \
     tcg_gen_gvec_3i(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
-                    vec_full_reg_offset(v3), c, 16, 16, gen)
+                    vec_full_reg_offset(v3), 16, 16, c, gen)
 #define gen_gvec_4(v1, v2, v3, v4, gen) \
     tcg_gen_gvec_4(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
                    vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
generated by git-patchbot for /home/xen/git/qemu-xen.git#staging-4.13



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