[xen staging] x86emul: SYSRET must change CPL

[patchbot@xxxxxxx]

commit a94b55a2986145ab5b357feb340f782d9d199d10
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Tue Apr 21 10:51:42 2020 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Tue Apr 21 10:51:42 2020 +0200

    x86emul: SYSRET must change CPL
    
    The special AMD behavior of leaving SS mostly alone wasn't really
    complete: We need to adjust CPL aka SS.DPL.
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/x86_emulate/x86_emulate.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c 
b/xen/arch/x86/x86_emulate/x86_emulate.c
index 3ed64c13ea..1959fc227a 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -6022,6 +6022,8 @@ x86_emulate(
 
             /* There's explicitly no RPL adjustment here. */
             sreg.sel = (msr_val >> 48) + 8;
+            /* But DPL needs adjustment, for the new CPL to be correct. */
+            sreg.dpl = 3;
         }
 
 #ifdef __x86_64__
--
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