[xen staging] x86/ucode/intel: Writeback and invalidate caches before updating microcode

[patchbot@xxxxxxx]

commit 77c82949990edaf21130be842a289a7fb7a439e1
Author:     Ashok Raj <ashok.raj@xxxxxxxxx>
AuthorDate: Wed Feb 28 10:28:42 2018 +0000
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Tue May 5 20:18:19 2020 +0100

    x86/ucode/intel: Writeback and invalidate caches before updating microcode
    
    Updating microcode is less error prone when caches have been flushed and
    depending on what exactly the microcode is updating. For example, some of 
the
    issues around certain Broadwell parts can be addressed by doing a full cache
    flush.
    
    Signed-off-by: Ashok Raj <ashok.raj@xxxxxxxxx>
    Signed-off-by: Borislav Petkov <bp@xxxxxxx>
    Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
    [Linux commit 91df9fdf51492aec9fed6b4cbd33160886740f47, ported to Xen]
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/cpu/microcode/intel.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/xen/arch/x86/cpu/microcode/intel.c 
b/xen/arch/x86/cpu/microcode/intel.c
index a9f4d6e829..d031196d4c 100644
--- a/xen/arch/x86/cpu/microcode/intel.c
+++ b/xen/arch/x86/cpu/microcode/intel.c
@@ -25,6 +25,7 @@
 #include <xen/init.h>
 
 #include <asm/msr.h>
+#include <asm/system.h>
 
 #include "private.h"
 
@@ -267,6 +268,8 @@ static int apply_microcode(const struct microcode_patch 
*patch)
     if ( microcode_update_match(patch) != NEW_UCODE )
         return -EINVAL;
 
+    wbinvd();
+
     /* write microcode via MSR 0x79 */
     wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)patch->data);
     wrmsrl(MSR_IA32_UCODE_REV, 0x0ULL);
--
generated by git-patchbot for /home/xen/git/xen.git#staging