[xen staging-4.12] x86/ucode/intel: Writeback and invalidate caches before updating microcode

[patchbot@xxxxxxx]

commit c26841f0aad0af887a6b3658d71959c4946e480d
Author:     Ashok Raj <ashok.raj@xxxxxxxxx>
AuthorDate: Thu May 7 14:58:16 2020 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Thu May 7 14:58:16 2020 +0200

    x86/ucode/intel: Writeback and invalidate caches before updating microcode
    
    Updating microcode is less error prone when caches have been flushed and
    depending on what exactly the microcode is updating. For example, some of 
the
    issues around certain Broadwell parts can be addressed by doing a full cache
    flush.
    
    Signed-off-by: Ashok Raj <ashok.raj@xxxxxxxxx>
    Signed-off-by: Borislav Petkov <bp@xxxxxxx>
    Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
    [Linux commit 91df9fdf51492aec9fed6b4cbd33160886740f47, ported to Xen]
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
    master commit: 77c82949990edaf21130be842a289a7fb7a439e1
    master date: 2020-05-05 20:18:19 +0100
---
 xen/arch/x86/microcode_intel.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/xen/arch/x86/microcode_intel.c b/xen/arch/x86/microcode_intel.c
index e511bd853c..f8e375a960 100644
--- a/xen/arch/x86/microcode_intel.c
+++ b/xen/arch/x86/microcode_intel.c
@@ -30,6 +30,7 @@
 
 #include <asm/msr.h>
 #include <asm/processor.h>
+#include <asm/system.h>
 #include <asm/microcode.h>
 
 #define pr_debug(x...) ((void)0)
@@ -294,6 +295,8 @@ static int apply_microcode(unsigned int cpu)
     /* serialize access to the physical write to MSR 0x79 */
     spin_lock_irqsave(&microcode_update_lock, flags);
 
+    wbinvd();
+
     /* write microcode via MSR 0x79 */
     wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)uci->mc.mc_intel->bits);
     wrmsrl(MSR_IA32_UCODE_REV, 0x0ULL);
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.12