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[xen stable-4.13] x86/ucode/intel: Writeback and invalidate caches before updating microcode

commit 9649b83b2ab4707de79da42307f8757e317bf217
Author:     Ashok Raj <ashok.raj@xxxxxxxxx>
AuthorDate: Thu May 7 14:51:20 2020 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Thu May 7 14:51:20 2020 +0200

    x86/ucode/intel: Writeback and invalidate caches before updating microcode
    Updating microcode is less error prone when caches have been flushed and
    depending on what exactly the microcode is updating. For example, some of 
    issues around certain Broadwell parts can be addressed by doing a full cache
    Signed-off-by: Ashok Raj <ashok.raj@xxxxxxxxx>
    Signed-off-by: Borislav Petkov <bp@xxxxxxx>
    Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
    [Linux commit 91df9fdf51492aec9fed6b4cbd33160886740f47, ported to Xen]
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
    master commit: 77c82949990edaf21130be842a289a7fb7a439e1
    master date: 2020-05-05 20:18:19 +0100
 xen/arch/x86/microcode_intel.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/xen/arch/x86/microcode_intel.c b/xen/arch/x86/microcode_intel.c
index e37c46a836..42fbd19551 100644
--- a/xen/arch/x86/microcode_intel.c
+++ b/xen/arch/x86/microcode_intel.c
@@ -30,6 +30,7 @@
 #include <asm/msr.h>
 #include <asm/processor.h>
+#include <asm/system.h>
 #include <asm/microcode.h>
 #define pr_debug(x...) ((void)0)
@@ -300,6 +301,8 @@ static int apply_microcode(const struct microcode_patch 
+    wbinvd();
     /* write microcode via MSR 0x79 */
     wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc_intel->bits);
     wrmsrl(MSR_IA32_UCODE_REV, 0x0ULL);
generated by git-patchbot for /home/xen/git/xen.git#stable-4.13



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