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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [xen staging] docs/migration: Specify X86_{CPUID,MSR}_POLICY records
commit ddd273d88632a0b20f80c20742d6759ed6b83c8b
Author: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Tue Dec 17 13:10:04 2019 +0000
Commit: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Fri May 29 17:33:03 2020 +0100
docs/migration: Specify X86_{CPUID,MSR}_POLICY records
These two records move blobs from the XEN_DOMCTL_{get,set}_cpu_policy
hypercall.
Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Acked-by: Ian Jackson <ian.jackson@xxxxxxxxxxxxx>
---
docs/specs/libxc-migration-stream.pandoc | 42 +++++++++++++++++++++++++++++++
tools/libxc/xc_sr_common.c | 2 ++
tools/libxc/xc_sr_stream_format.h | 2 ++
tools/python/xen/migration/libxc.py | 43 ++++++++++++++++++++++++++++++++
4 files changed, 89 insertions(+)
diff --git a/docs/specs/libxc-migration-stream.pandoc
b/docs/specs/libxc-migration-stream.pandoc
index 346d243175..6b0c49e97a 100644
--- a/docs/specs/libxc-migration-stream.pandoc
+++ b/docs/specs/libxc-migration-stream.pandoc
@@ -634,6 +634,46 @@ The end record contains no fields; its body_length is 0.
\clearpage
+X86_CPUID_POLICY
+----------------
+
+CPUID policy content, as accessed by the XEN_DOMCTL_{get,set}_cpu_policy
+hypercall sub-ops.
+
+ 0 1 2 3 4 5 6 7 octet
+ +-------------------------------------------------+
+ | CPUID_policy |
+ ...
+ +-------------------------------------------------+
+
+--------------------------------------------------------------------
+Field Description
+------------ ---------------------------------------------------
+CPUID_policy Array of xen_cpuid_leaf_t[]'s
+--------------------------------------------------------------------
+
+\clearpage
+
+X86_MSR_POLICY
+--------------
+
+MSR policy content, as accessed by the XEN_DOMCTL_{get,set}_cpu_policy
+hypercall sub-ops.
+
+ 0 1 2 3 4 5 6 7 octet
+ +-------------------------------------------------+
+ | MSR_policy |
+ ...
+ +-------------------------------------------------+
+
+--------------------------------------------------------------------
+Field Description
+---------- ---------------------------------------------------
+MSR_policy Array of xen_msr_entry_t[]'s
+--------------------------------------------------------------------
+
+\clearpage
+
Layout
======
@@ -656,6 +696,7 @@ A typical save record for an x86 PV guest image would look
like:
* Domain header
* Static data records:
* X86_PV_INFO record
+ * X86_{CPUID,MSR}_POLICY
* STATIC_DATA_END
* X86_PV_P2M_FRAMES record
* Many PAGE_DATA records
@@ -685,6 +726,7 @@ A typical save record for an x86 HVM guest image would look
like:
* Image header
* Domain header
* Static data records:
+ * X86_{CPUID,MSR}_POLICY
* STATIC_DATA_END
* Many PAGE_DATA records
* X86_TSC_INFO
diff --git a/tools/libxc/xc_sr_common.c b/tools/libxc/xc_sr_common.c
index 7f22cf0365..7c54b03414 100644
--- a/tools/libxc/xc_sr_common.c
+++ b/tools/libxc/xc_sr_common.c
@@ -37,6 +37,8 @@ static const char *const mandatory_rec_types[] =
[REC_TYPE_CHECKPOINT] = "Checkpoint",
[REC_TYPE_CHECKPOINT_DIRTY_PFN_LIST] = "Checkpoint dirty pfn list",
[REC_TYPE_STATIC_DATA_END] = "Static data end",
+ [REC_TYPE_X86_CPUID_POLICY] = "x86 CPUID policy",
+ [REC_TYPE_X86_MSR_POLICY] = "x86 MSR policy",
};
const char *rec_type_to_str(uint32_t type)
diff --git a/tools/libxc/xc_sr_stream_format.h
b/tools/libxc/xc_sr_stream_format.h
index 81c9765b0a..8a0da26f75 100644
--- a/tools/libxc/xc_sr_stream_format.h
+++ b/tools/libxc/xc_sr_stream_format.h
@@ -74,6 +74,8 @@ struct xc_sr_rhdr
#define REC_TYPE_CHECKPOINT 0x0000000eU
#define REC_TYPE_CHECKPOINT_DIRTY_PFN_LIST 0x0000000fU
#define REC_TYPE_STATIC_DATA_END 0x00000010U
+#define REC_TYPE_X86_CPUID_POLICY 0x00000011U
+#define REC_TYPE_X86_MSR_POLICY 0x00000012U
#define REC_TYPE_OPTIONAL 0x80000000U
diff --git a/tools/python/xen/migration/libxc.py
b/tools/python/xen/migration/libxc.py
index 5fb51b56ac..9881f5ced4 100644
--- a/tools/python/xen/migration/libxc.py
+++ b/tools/python/xen/migration/libxc.py
@@ -57,6 +57,8 @@ REC_TYPE_verify = 0x0000000d
REC_TYPE_checkpoint = 0x0000000e
REC_TYPE_checkpoint_dirty_pfn_list = 0x0000000f
REC_TYPE_static_data_end = 0x00000010
+REC_TYPE_x86_cpuid_policy = 0x00000011
+REC_TYPE_x86_msr_policy = 0x00000012
rec_type_to_str = {
REC_TYPE_end : "End",
@@ -76,6 +78,8 @@ rec_type_to_str = {
REC_TYPE_checkpoint : "Checkpoint",
REC_TYPE_checkpoint_dirty_pfn_list : "Checkpoint dirty pfn list",
REC_TYPE_static_data_end : "Static data end",
+ REC_TYPE_x86_cpuid_policy : "x86 CPUID policy",
+ REC_TYPE_x86_msr_policy : "x86 MSR policy",
}
# page_data
@@ -113,6 +117,12 @@ X86_TSC_INFO_FORMAT = "IIQII"
HVM_PARAMS_ENTRY_FORMAT = "QQ"
HVM_PARAMS_FORMAT = "II"
+# x86_cpuid_policy => xen_cpuid_leaf_t[]
+X86_CPUID_POLICY_FORMAT = "IIIIII"
+
+# x86_msr_policy => xen_msr_entry_t[]
+X86_MSR_POLICY_FORMAT = "QII"
+
class VerifyLibxc(VerifyBase):
""" Verify a Libxc v2 (or later) stream """
@@ -439,6 +449,34 @@ class VerifyLibxc(VerifyBase):
raise RecordError("Static data end record found in v2 stream")
+ def verify_record_x86_cpuid_policy(self, content):
+ """ x86 CPUID policy record """
+
+ if self.version < 3:
+ raise RecordError("x86 CPUID policy record found in v2 stream")
+
+ sz = calcsize(X86_CPUID_POLICY_FORMAT)
+ contentsz = len(content)
+
+ if contentsz < sz or (contentsz % sz) != 0:
+ raise RecordError("Record length %u, expected multiple of %u" %
+ (contentsz, sz))
+
+
+ def verify_record_x86_msr_policy(self, content):
+ """ x86 MSR policy record """
+
+ if self.version < 3:
+ raise RecordError("x86 MSR policy record found in v2 stream")
+
+ sz = calcsize(X86_MSR_POLICY_FORMAT)
+ contentsz = len(content)
+
+ if contentsz < sz or (contentsz % sz) != 0:
+ raise RecordError("Record length %u, expected multiple of %u" %
+ (contentsz, sz))
+
+
record_verifiers = {
REC_TYPE_end:
VerifyLibxc.verify_record_end,
@@ -483,4 +521,9 @@ record_verifiers = {
REC_TYPE_static_data_end:
VerifyLibxc.verify_record_static_data_end,
+
+ REC_TYPE_x86_cpuid_policy:
+ VerifyLibxc.verify_record_x86_cpuid_policy,
+ REC_TYPE_x86_msr_policy:
+ VerifyLibxc.verify_record_x86_msr_policy,
}
--
generated by git-patchbot for /home/xen/git/xen.git#staging
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