[xen staging] x86/Intel: insert Ice Lake and Comet Lake model numbers

[patchbot@xxxxxxx]

commit 1fe406685cb19e9544681c6243e7d376deb0297e
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Tue Jun 9 12:55:53 2020 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Tue Jun 9 12:55:53 2020 +0200

    x86/Intel: insert Ice Lake and Comet Lake model numbers
    
    Both match prior generation processors as far as LBR and C-state MSRs
    go (SDM rev 072) as well as applicability of the if_pschange_mc erratum
    (recent spec updates).
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Reviewed-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
    Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Release-acked-by: Paul Durrant <paul@xxxxxxx>
---
 xen/arch/x86/acpi/cpu_idle.c | 6 ++++++
 xen/arch/x86/hvm/vmx/vmx.c   | 8 ++++++++
 2 files changed, 14 insertions(+)

diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index a2248ea11f..27e0b52621 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -180,9 +180,15 @@ static void do_get_hw_residencies(void *arg)
     case 0x4E:
     case 0x55:
     case 0x5E:
+    /* Ice Lake */
+    case 0x7D:
+    case 0x7E:
     /* Kaby Lake */
     case 0x8E:
     case 0x9E:
+    /* Comet Lake */
+    case 0xA5:
+    case 0xA6:
         GET_PC2_RES(hw_res->pc2);
         GET_CC7_RES(hw_res->cc7);
         /* fall through */
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index b7d0c58214..ab19d9424e 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -2438,8 +2438,12 @@ static bool __init has_if_pschange_mc(void)
     case 0x4e: /* Skylake M */
     case 0x5e: /* Skylake D */
     case 0x55: /* Skylake-X / Cascade Lake */
+    case 0x7d: /* Ice Lake */
+    case 0x7e: /* Ice Lake */
     case 0x8e: /* Kaby / Coffee / Whiskey Lake M */
     case 0x9e: /* Kaby / Coffee / Whiskey Lake D */
+    case 0xa5: /* Comet Lake H/S */
+    case 0xa6: /* Comet Lake U */
         return true;
 
         /*
@@ -2781,10 +2785,14 @@ static const struct lbr_info *last_branch_msr_get(void)
         case 0x66:
         /* Goldmont Plus */
         case 0x7a:
+        /* Ice Lake */
+        case 0x7d: case 0x7e:
         /* Tremont */
         case 0x86:
         /* Kaby Lake */
         case 0x8e: case 0x9e:
+        /* Comet Lake */
+        case 0xa5: case 0xa6:
             return sk_lbr;
         /* Atom */
         case 0x1c: case 0x26: case 0x27: case 0x35: case 0x36:
--
generated by git-patchbot for /home/xen/git/xen.git#staging