[xen staging-4.13] x86/pv: Handle the Intel-specific MSR_MISC_ENABLE correctly

[patchbot@xxxxxxx]

commit b98031951d19b9576a2200859bae86119c1e681c
Author:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Tue Sep 22 16:20:09 2020 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Tue Sep 22 16:20:09 2020 +0200

    x86/pv: Handle the Intel-specific MSR_MISC_ENABLE correctly
    
    This MSR doesn't exist on AMD hardware, and switching away from the safe
    functions in the common MSR path was an erroneous change.
    
    Partially revert the change.
    
    This is XSA-333.
    
    Fixes: 4fdc932b3cc ("x86/Intel: drop another 32-bit leftover")
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
    Reviewed-by: Wei Liu <wl@xxxxxxx>
---
 xen/arch/x86/pv/emul-priv-op.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index 9a5b3edfae..42258c6bf1 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -869,7 +869,8 @@ static int read_msr(unsigned int reg, uint64_t *val,
         return X86EMUL_OKAY;
 
     case MSR_IA32_MISC_ENABLE:
-        rdmsrl(reg, *val);
+        if ( rdmsr_safe(reg, *val) )
+            break;
         *val = guest_misc_enable(*val);
         return X86EMUL_OKAY;
 
@@ -1009,7 +1010,8 @@ static int write_msr(unsigned int reg, uint64_t val,
         break;
 
     case MSR_IA32_MISC_ENABLE:
-        rdmsrl(reg, temp);
+        if ( rdmsr_safe(reg, temp) )
+            break;
         if ( val != guest_misc_enable(temp) )
             goto invalid;
         return X86EMUL_OKAY;
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.13