[xen master] x86/svm: ignore accesses to EX_CFG

[patchbot@xxxxxxx]

commit 5164e44885252ae909977dd3b39c743544f3f5f0
Author:     Roger Pau Monné <roger.pau@xxxxxxxxxx>
AuthorDate: Mon Sep 21 12:11:38 2020 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Mon Sep 21 12:11:38 2020 +0200

    x86/svm: ignore accesses to EX_CFG
    
    Windows 10 will try to unconditionally read (and possibly even adjust)
    EX_CFG on AMD hardware, despite it being documented only for Fam15 models
    0xh, and injecting a #GP fault will result in a panic:
    
    svm.c:1964:d5v0 RDMSR 0xc001102c unimplemented
    d5v0 VIRIDIAN CRASH: 7e ffffffffc0000096 fffff8054cbe5ffe fffffa0837a066e8 
fffffa0837a05f30
    
    Return 0 when trying to read the MSR and drop writes.
    
    Fixes: 84e848fd7a16 ('x86/hvm: disallow access to unknown MSRs')
    Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/hvm/svm/svm.c      | 2 ++
 xen/include/asm-x86/msr-index.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index 136445972e..5037c0fe7d 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -1942,6 +1942,7 @@ static int svm_msr_read_intercept(unsigned int msr, 
uint64_t *msr_content)
     case MSR_K8_TOP_MEM1:
     case MSR_K8_TOP_MEM2:
     case MSR_K8_VM_CR:
+    case MSR_AMD64_EX_CFG:
         *msr_content = 0;
         break;
 
@@ -2108,6 +2109,7 @@ static int svm_msr_write_intercept(unsigned int msr, 
uint64_t msr_content)
     case MSR_K8_TOP_MEM2:
     case MSR_K8_SYSCFG:
     case MSR_K8_VM_CR:
+    case MSR_AMD64_EX_CFG:
         /* ignore write. handle all bits as read-only. */
         break;
 
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 4fd54fb5c9..3e0c6c8476 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -330,6 +330,7 @@
 #define MSR_AMD64_DC_CFG               0xc0011022
 #define MSR_AMD64_DE_CFG               0xc0011029
 #define AMD64_DE_CFG_LFENCE_SERIALISE  (_AC(1, ULL) << 1)
+#define MSR_AMD64_EX_CFG               0xc001102c
 
 #define MSR_AMD64_DR0_ADDRESS_MASK     0xc0011027
 #define MSR_AMD64_DR1_ADDRESS_MASK     0xc0011019
--
generated by git-patchbot for /home/xen/git/xen.git#master